137586e0bSZhangfei Gao* MARVELL MMP DMA controller 237586e0bSZhangfei Gao 337586e0bSZhangfei GaoMarvell Peripheral DMA Controller 437586e0bSZhangfei GaoUsed platfroms: pxa688, pxa910, pxa3xx, etc 537586e0bSZhangfei Gao 637586e0bSZhangfei GaoRequired properties: 737586e0bSZhangfei Gao- compatible: Should be "marvell,pdma-1.0" 837586e0bSZhangfei Gao- reg: Should contain DMA registers location and length. 937586e0bSZhangfei Gao- interrupts: Either contain all of the per-channel DMA interrupts 1037586e0bSZhangfei Gao or one irq for pdma device 1137586e0bSZhangfei Gao- #dma-channels: Number of DMA channels supported by the controller. 1237586e0bSZhangfei Gao 1337586e0bSZhangfei Gao"marvell,pdma-1.0" 1437586e0bSZhangfei GaoUsed platfroms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688. 1537586e0bSZhangfei Gao 1637586e0bSZhangfei GaoExamples: 1737586e0bSZhangfei Gao 1837586e0bSZhangfei Gao/* 1937586e0bSZhangfei Gao * Each channel has specific irq 2037586e0bSZhangfei Gao * ICU parse out irq channel from ICU register, 2137586e0bSZhangfei Gao * while DMA controller may not able to distinguish the irq channel 2237586e0bSZhangfei Gao * Using this method, interrupt-parent is required as demuxer 2337586e0bSZhangfei Gao * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq, 2437586e0bSZhangfei Gao * 18~21 is ADMA irq 2537586e0bSZhangfei Gao */ 2637586e0bSZhangfei Gaopdma: dma-controller@d4000000 { 2737586e0bSZhangfei Gao compatible = "marvell,pdma-1.0"; 2837586e0bSZhangfei Gao reg = <0xd4000000 0x10000>; 2937586e0bSZhangfei Gao interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; 3037586e0bSZhangfei Gao interrupt-parent = <&intcmux32>; 3137586e0bSZhangfei Gao #dma-channels = <16>; 3237586e0bSZhangfei Gao }; 3337586e0bSZhangfei Gao 3437586e0bSZhangfei Gao/* 3537586e0bSZhangfei Gao * One irq for all channels 3637586e0bSZhangfei Gao * Dmaengine driver (DMA controller) distinguish irq channel via 3737586e0bSZhangfei Gao * parsing internal register 3837586e0bSZhangfei Gao */ 3937586e0bSZhangfei Gaopdma: dma-controller@d4000000 { 4037586e0bSZhangfei Gao compatible = "marvell,pdma-1.0"; 4137586e0bSZhangfei Gao reg = <0xd4000000 0x10000>; 4237586e0bSZhangfei Gao interrupts = <47>; 4337586e0bSZhangfei Gao #dma-channels = <16>; 4437586e0bSZhangfei Gao }; 4537586e0bSZhangfei Gao 4637586e0bSZhangfei Gao 4737586e0bSZhangfei GaoMarvell Two Channel DMA Controller used specifically for audio 4837586e0bSZhangfei GaoUsed platfroms: pxa688, pxa910 4937586e0bSZhangfei Gao 5037586e0bSZhangfei GaoRequired properties: 5137586e0bSZhangfei Gao- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ" 5237586e0bSZhangfei Gao- reg: Should contain DMA registers location and length. 5337586e0bSZhangfei Gao- interrupts: Either contain all of the per-channel DMA interrupts 5437586e0bSZhangfei Gao or one irq for dma device 5537586e0bSZhangfei Gao 5637586e0bSZhangfei Gao"marvell,adma-1.0" used on pxa688 5737586e0bSZhangfei Gao"marvell,pxa910-squ" used on pxa910 5837586e0bSZhangfei Gao 5937586e0bSZhangfei GaoExamples: 6037586e0bSZhangfei Gao 6137586e0bSZhangfei Gao/* each channel has specific irq */ 6237586e0bSZhangfei Gaoadma0: dma-controller@d42a0800 { 6337586e0bSZhangfei Gao compatible = "marvell,adma-1.0"; 6437586e0bSZhangfei Gao reg = <0xd42a0800 0x100>; 6537586e0bSZhangfei Gao interrupts = <18 19>; 6637586e0bSZhangfei Gao interrupt-parent = <&intcmux32>; 6737586e0bSZhangfei Gao }; 6837586e0bSZhangfei Gao 6937586e0bSZhangfei Gao/* One irq for all channels */ 7037586e0bSZhangfei Gaosqu: dma-controller@d42a0800 { 7137586e0bSZhangfei Gao compatible = "marvell,pxa910-squ"; 7237586e0bSZhangfei Gao reg = <0xd42a0800 0x100>; 7337586e0bSZhangfei Gao interrupts = <46>; 7437586e0bSZhangfei Gao }; 75