13708f89bSJassi Brar* Milbeaut AXI DMA Controller
23708f89bSJassi Brar
33708f89bSJassi BrarMilbeaut AXI DMA controller has only memory to memory transfer capability.
43708f89bSJassi Brar
53708f89bSJassi Brar* DMA controller
63708f89bSJassi Brar
73708f89bSJassi BrarRequired property:
83708f89bSJassi Brar- compatible: 	Should be  "socionext,milbeaut-m10v-xdmac"
93708f89bSJassi Brar- reg:		Should contain DMA registers location and length.
103708f89bSJassi Brar- interrupts: 	Should contain all of the per-channel DMA interrupts.
113708f89bSJassi Brar                Number of channels is configurable - 2, 4 or 8, so
123708f89bSJassi Brar                the number of interrupts specified should be {2,4,8}.
133708f89bSJassi Brar- #dma-cells: 	Should be 1.
143708f89bSJassi Brar
153708f89bSJassi BrarExample:
163708f89bSJassi Brar	xdmac0: dma-controller@1c250000 {
173708f89bSJassi Brar		compatible = "socionext,milbeaut-m10v-xdmac";
183708f89bSJassi Brar		reg = <0x1c250000 0x1000>;
193708f89bSJassi Brar		interrupts = <0 17 0x4>,
203708f89bSJassi Brar			     <0 18 0x4>,
213708f89bSJassi Brar			     <0 19 0x4>,
223708f89bSJassi Brar			     <0 20 0x4>;
233708f89bSJassi Brar		#dma-cells = <1>;
243708f89bSJassi Brar	};
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