1NXP Layerscape SoC qDMA Controller 2================================== 3 4This device follows the generic DMA bindings defined in dma/dma.txt. 5 6Required properties: 7 8- compatible: Must be one of 9 "fsl,ls1021a-qdma": for LS1021A Board 10 "fsl,ls1043a-qdma": for ls1043A Board 11 "fsl,ls1046a-qdma": for ls1046A Board 12- reg: Should contain the register's base address and length. 13- interrupts: Should contain a reference to the interrupt used by this 14 device. 15- interrupt-names: Should contain interrupt names: 16 "qdma-queue0": the block0 interrupt 17 "qdma-queue1": the block1 interrupt 18 "qdma-queue2": the block2 interrupt 19 "qdma-queue3": the block3 interrupt 20 "qdma-error": the error interrupt 21- fsl,dma-queues: Should contain number of queues supported. 22- dma-channels: Number of DMA channels supported 23- block-number: the virtual block number 24- block-offset: the offset of different virtual block 25- status-sizes: status queue size of per virtual block 26- queue-sizes: command queue size of per virtual block, the size number 27 based on queues 28 29Optional properties: 30 31- dma-channels: Number of DMA channels supported by the controller. 32- big-endian: If present registers and hardware scatter/gather descriptors 33 of the qDMA are implemented in big endian mode, otherwise in little 34 mode. 35 36Examples: 37 38 qdma: dma-controller@8390000 { 39 compatible = "fsl,ls1021a-qdma"; 40 reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */ 41 <0x0 0x8389000 0x0 0x1000>, /* Status regs */ 42 <0x0 0x838a000 0x0 0x2000>; /* Block regs */ 43 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 46 interrupt-names = "qdma-error", 47 "qdma-queue0", "qdma-queue1"; 48 dma-channels = <8>; 49 block-number = <2>; 50 block-offset = <0x1000>; 51 fsl,dma-queues = <2>; 52 status-sizes = <64>; 53 queue-sizes = <64 64>; 54 big-endian; 55 }; 56 57DMA clients must use the format described in dma/dma.txt file. 58