1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright 2019 Texas Instruments Incorporated
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Texas Instruments AM65x Display Subsystem
9
10maintainers:
11  - Jyri Sarha <jsarha@ti.com>
12  - Tomi Valkeinen <tomi.valkeinen@ti.com>
13
14description: |
15  The AM625 and AM65x TI Keystone Display SubSystem with two output
16  ports and two video planes. In AM65x DSS, the first video port
17  supports 1 OLDI TX and in AM625 DSS, the first video port output is
18  internally routed to 2 OLDI TXes. The second video port supports DPI
19  format. The first plane is full video plane with all features and the
20  second is a "lite plane" without scaling support.
21
22properties:
23  compatible:
24    enum:
25      - ti,am625-dss
26      - ti,am65x-dss
27
28  reg:
29    description:
30      Addresses to each DSS memory region described in the SoC's TRM.
31    items:
32      - description: common DSS register area
33      - description: VIDL1 light video plane
34      - description: VID video plane
35      - description: OVR1 overlay manager for vp1
36      - description: OVR2 overlay manager for vp2
37      - description: VP1 video port 1
38      - description: VP2 video port 2
39
40  reg-names:
41    items:
42      - const: common
43      - const: vidl1
44      - const: vid
45      - const: ovr1
46      - const: ovr2
47      - const: vp1
48      - const: vp2
49
50  clocks:
51    items:
52      - description: fck DSS functional clock
53      - description: vp1 Video Port 1 pixel clock
54      - description: vp2 Video Port 2 pixel clock
55
56  clock-names:
57    items:
58      - const: fck
59      - const: vp1
60      - const: vp2
61
62  assigned-clocks:
63    minItems: 1
64    maxItems: 3
65
66  assigned-clock-parents:
67    minItems: 1
68    maxItems: 3
69
70  interrupts:
71    maxItems: 1
72
73  power-domains:
74    maxItems: 1
75    description: phandle to the associated power domain
76
77  dma-coherent:
78    type: boolean
79
80  ports:
81    $ref: /schemas/graph.yaml#/properties/ports
82
83    properties:
84      port@0:
85        $ref: /schemas/graph.yaml#/properties/port
86        description:
87          For AM65x DSS, the OLDI output port node from video port 1.
88          For AM625 DSS, the internal DPI output port node from video
89          port 1.
90
91      port@1:
92        $ref: /schemas/graph.yaml#/properties/port
93        description:
94          The DSS DPI output port node from video port 2
95
96  ti,am65x-oldi-io-ctrl:
97    $ref: /schemas/types.yaml#/definitions/phandle
98    description:
99      phandle to syscon device node mapping OLDI IO_CTRL registers.
100      The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
101      following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL,
102      and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
103      interface to work.
104
105  max-memory-bandwidth:
106    $ref: /schemas/types.yaml#/definitions/uint32
107    description:
108      Input memory (from main memory to dispc) bandwidth limit in
109      bytes per second
110
111required:
112  - compatible
113  - reg
114  - reg-names
115  - clocks
116  - clock-names
117  - interrupts
118  - ports
119
120additionalProperties: false
121
122examples:
123  - |
124    #include <dt-bindings/interrupt-controller/arm-gic.h>
125    #include <dt-bindings/interrupt-controller/irq.h>
126    #include <dt-bindings/soc/ti,sci_pm_domain.h>
127
128    dss: dss@4a00000 {
129            compatible = "ti,am65x-dss";
130            reg =   <0x04a00000 0x1000>, /* common */
131                    <0x04a02000 0x1000>, /* vidl1 */
132                    <0x04a06000 0x1000>, /* vid */
133                    <0x04a07000 0x1000>, /* ovr1 */
134                    <0x04a08000 0x1000>, /* ovr2 */
135                    <0x04a0a000 0x1000>, /* vp1 */
136                    <0x04a0b000 0x1000>; /* vp2 */
137            reg-names = "common", "vidl1", "vid",
138                    "ovr1", "ovr2", "vp1", "vp2";
139            ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
140            power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
141            clocks =        <&k3_clks 67 1>,
142                            <&k3_clks 216 1>,
143                            <&k3_clks 67 2>;
144            clock-names = "fck", "vp1", "vp2";
145            interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
146            ports {
147                    #address-cells = <1>;
148                    #size-cells = <0>;
149                    port@0 {
150                            reg = <0>;
151                            oldi_out0: endpoint {
152                                    remote-endpoint = <&lcd_in0>;
153                            };
154                    };
155            };
156    };
157