1*fe8b45aaSThierry Reding# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*fe8b45aaSThierry Reding%YAML 1.2 3*fe8b45aaSThierry Reding--- 4*fe8b45aaSThierry Reding$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-isp.yaml# 5*fe8b45aaSThierry Reding$schema: http://devicetree.org/meta-schemas/core.yaml# 6*fe8b45aaSThierry Reding 7*fe8b45aaSThierry Redingtitle: NVIDIA Tegra ISP processor 8*fe8b45aaSThierry Reding 9*fe8b45aaSThierry Redingmaintainers: 10*fe8b45aaSThierry Reding - Thierry Reding <thierry.reding@gmail.com> 11*fe8b45aaSThierry Reding - Jon Hunter <jonathanh@nvidia.com> 12*fe8b45aaSThierry Reding 13*fe8b45aaSThierry Redingproperties: 14*fe8b45aaSThierry Reding compatible: 15*fe8b45aaSThierry Reding enum: 16*fe8b45aaSThierry Reding - nvidia,tegra20-isp 17*fe8b45aaSThierry Reding - nvidia,tegra30-isp 18*fe8b45aaSThierry Reding - nvidia,tegra210-isp 19*fe8b45aaSThierry Reding 20*fe8b45aaSThierry Reding reg: 21*fe8b45aaSThierry Reding maxItems: 1 22*fe8b45aaSThierry Reding 23*fe8b45aaSThierry Reding interrupts: 24*fe8b45aaSThierry Reding maxItems: 1 25*fe8b45aaSThierry Reding 26*fe8b45aaSThierry Reding clocks: 27*fe8b45aaSThierry Reding items: 28*fe8b45aaSThierry Reding - description: module clock 29*fe8b45aaSThierry Reding 30*fe8b45aaSThierry Reding resets: 31*fe8b45aaSThierry Reding items: 32*fe8b45aaSThierry Reding - description: module reset 33*fe8b45aaSThierry Reding 34*fe8b45aaSThierry Reding reset-names: 35*fe8b45aaSThierry Reding items: 36*fe8b45aaSThierry Reding - const: isp 37*fe8b45aaSThierry Reding 38*fe8b45aaSThierry Reding iommus: 39*fe8b45aaSThierry Reding maxItems: 1 40*fe8b45aaSThierry Reding 41*fe8b45aaSThierry Reding interconnects: 42*fe8b45aaSThierry Reding items: 43*fe8b45aaSThierry Reding - description: memory write client 44*fe8b45aaSThierry Reding 45*fe8b45aaSThierry Reding interconnect-names: 46*fe8b45aaSThierry Reding items: 47*fe8b45aaSThierry Reding - const: dma-mem # write 48*fe8b45aaSThierry Reding 49*fe8b45aaSThierry Reding power-domains: 50*fe8b45aaSThierry Reding items: 51*fe8b45aaSThierry Reding - description: phandle to the VENC or core power domain 52*fe8b45aaSThierry Reding 53*fe8b45aaSThierry RedingadditionalProperties: false 54*fe8b45aaSThierry Reding 55*fe8b45aaSThierry Redingexamples: 56*fe8b45aaSThierry Reding - | 57*fe8b45aaSThierry Reding #include <dt-bindings/clock/tegra20-car.h> 58*fe8b45aaSThierry Reding #include <dt-bindings/interrupt-controller/arm-gic.h> 59*fe8b45aaSThierry Reding 60*fe8b45aaSThierry Reding isp@54100000 { 61*fe8b45aaSThierry Reding compatible = "nvidia,tegra20-isp"; 62*fe8b45aaSThierry Reding reg = <0x54100000 0x00040000>; 63*fe8b45aaSThierry Reding interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 64*fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA20_CLK_ISP>; 65*fe8b45aaSThierry Reding resets = <&tegra_car 23>; 66*fe8b45aaSThierry Reding reset-names = "isp"; 67*fe8b45aaSThierry Reding }; 68