1fe8b45aaSThierry Reding# SPDX-License-Identifier: GPL-2.0-only 2fe8b45aaSThierry Reding%YAML 1.2 3fe8b45aaSThierry Reding--- 4fe8b45aaSThierry Reding$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml# 5fe8b45aaSThierry Reding$schema: http://devicetree.org/meta-schemas/core.yaml# 6fe8b45aaSThierry Reding 7fe8b45aaSThierry Redingtitle: NVIDIA Tegra host1x controller 8fe8b45aaSThierry Reding 9fe8b45aaSThierry Redingmaintainers: 10fe8b45aaSThierry Reding - Thierry Reding <thierry.reding@gmail.com> 11fe8b45aaSThierry Reding - Jon Hunter <jonathanh@nvidia.com> 12fe8b45aaSThierry Reding 13fe8b45aaSThierry Redingdescription: The host1x top-level node defines a number of children, each 14fe8b45aaSThierry Reding representing one of the host1x client modules defined in this binding. 15fe8b45aaSThierry Reding 16fe8b45aaSThierry Redingproperties: 17fe8b45aaSThierry Reding compatible: 18fe8b45aaSThierry Reding oneOf: 19fe8b45aaSThierry Reding - enum: 20fe8b45aaSThierry Reding - nvidia,tegra20-host1x 21fe8b45aaSThierry Reding - nvidia,tegra30-host1x 22fe8b45aaSThierry Reding - nvidia,tegra114-host1x 23fe8b45aaSThierry Reding - nvidia,tegra124-host1x 24fe8b45aaSThierry Reding - nvidia,tegra210-host1x 25fe8b45aaSThierry Reding - nvidia,tegra186-host1x 26fe8b45aaSThierry Reding - nvidia,tegra194-host1x 27fe8b45aaSThierry Reding 28fe8b45aaSThierry Reding - items: 29fe8b45aaSThierry Reding - const: nvidia,tegra132-host1x 30fe8b45aaSThierry Reding - const: nvidia,tegra124-host1x 31fe8b45aaSThierry Reding 32fe8b45aaSThierry Reding reg: 33fe8b45aaSThierry Reding minItems: 1 34fe8b45aaSThierry Reding maxItems: 2 35fe8b45aaSThierry Reding 36fe8b45aaSThierry Reding reg-names: 37fe8b45aaSThierry Reding minItems: 1 38fe8b45aaSThierry Reding maxItems: 2 39fe8b45aaSThierry Reding 40fe8b45aaSThierry Reding interrupts: 41fe8b45aaSThierry Reding items: 42fe8b45aaSThierry Reding - description: host1x syncpoint interrupt 43fe8b45aaSThierry Reding - description: host1x general interrupt 44fe8b45aaSThierry Reding minItems: 1 45fe8b45aaSThierry Reding 46fe8b45aaSThierry Reding interrupt-names: 47fe8b45aaSThierry Reding items: 48fe8b45aaSThierry Reding - const: syncpt 49fe8b45aaSThierry Reding - const: host1x 50fe8b45aaSThierry Reding minItems: 1 51fe8b45aaSThierry Reding 52fe8b45aaSThierry Reding '#address-cells': 53fe8b45aaSThierry Reding description: The number of cells used to represent physical base addresses 54fe8b45aaSThierry Reding in the host1x address space. 55fe8b45aaSThierry Reding enum: [1, 2] 56fe8b45aaSThierry Reding 57fe8b45aaSThierry Reding '#size-cells': 58fe8b45aaSThierry Reding description: The number of cells used to represent the size of an address 59fe8b45aaSThierry Reding range in the host1x address space. 60fe8b45aaSThierry Reding enum: [1, 2] 61fe8b45aaSThierry Reding 62fe8b45aaSThierry Reding ranges: 63fe8b45aaSThierry Reding maxItems: 1 64fe8b45aaSThierry Reding 65fe8b45aaSThierry Reding clocks: 66fe8b45aaSThierry Reding description: Must contain one entry, for the module clock. See 67fe8b45aaSThierry Reding ../clocks/clock-bindings.txt for details. 68fe8b45aaSThierry Reding 69fe8b45aaSThierry Reding clock-names: 70fe8b45aaSThierry Reding items: 71fe8b45aaSThierry Reding - const: host1x 72fe8b45aaSThierry Reding 73fe8b45aaSThierry Reding resets: 74fe8b45aaSThierry Reding minItems: 1 # MC reset is optional on Tegra186 and later 75fe8b45aaSThierry Reding items: 76fe8b45aaSThierry Reding - description: module reset 77fe8b45aaSThierry Reding - description: memory client hotflush reset 78fe8b45aaSThierry Reding 79fe8b45aaSThierry Reding reset-names: 80fe8b45aaSThierry Reding minItems: 1 # MC reset is optional on Tegra186 and later 81fe8b45aaSThierry Reding items: 82fe8b45aaSThierry Reding - const: host1x 83fe8b45aaSThierry Reding - const: mc 84fe8b45aaSThierry Reding 85fe8b45aaSThierry Reding iommus: 86fe8b45aaSThierry Reding maxItems: 1 87fe8b45aaSThierry Reding 88fe8b45aaSThierry Reding interconnects: 89fe8b45aaSThierry Reding items: 90fe8b45aaSThierry Reding - description: memory read client for host1x 91fe8b45aaSThierry Reding 92fe8b45aaSThierry Reding interconnect-names: 93fe8b45aaSThierry Reding items: 94fe8b45aaSThierry Reding - const: dma-mem # read 95fe8b45aaSThierry Reding 96fe8b45aaSThierry Reding operating-points-v2: 97fe8b45aaSThierry Reding $ref: "/schemas/types.yaml#/definitions/phandle" 98fe8b45aaSThierry Reding 99fe8b45aaSThierry Reding power-domains: 100fe8b45aaSThierry Reding items: 101fe8b45aaSThierry Reding - description: phandle to the HEG or core power domain 102fe8b45aaSThierry Reding 103fe8b45aaSThierry Redingrequired: 104fe8b45aaSThierry Reding - compatible 105fe8b45aaSThierry Reding - interrupts 106fe8b45aaSThierry Reding - interrupt-names 107fe8b45aaSThierry Reding - '#address-cells' 108fe8b45aaSThierry Reding - '#size-cells' 109fe8b45aaSThierry Reding - ranges 110fe8b45aaSThierry Reding - reg 111fe8b45aaSThierry Reding - clocks 112fe8b45aaSThierry Reding - clock-names 113fe8b45aaSThierry Reding - resets 114fe8b45aaSThierry Reding - reset-names 115fe8b45aaSThierry Reding 116fe8b45aaSThierry RedingunevaluatedProperties: 117fe8b45aaSThierry Reding type: object 118fe8b45aaSThierry Reding 119fe8b45aaSThierry RedingallOf: 120fe8b45aaSThierry Reding - if: 121fe8b45aaSThierry Reding properties: 122fe8b45aaSThierry Reding compatible: 123fe8b45aaSThierry Reding contains: 124fe8b45aaSThierry Reding enum: 125fe8b45aaSThierry Reding - nvidia,tegra186-host1x 126fe8b45aaSThierry Reding - nvidia,tegra194-host1x 127fe8b45aaSThierry Reding then: 128fe8b45aaSThierry Reding properties: 129fe8b45aaSThierry Reding reg-names: 130fe8b45aaSThierry Reding items: 131fe8b45aaSThierry Reding - const: hypervisor 132fe8b45aaSThierry Reding - const: vm 133fe8b45aaSThierry Reding 134fe8b45aaSThierry Reding reg: 135fe8b45aaSThierry Reding items: 136fe8b45aaSThierry Reding - description: physical base address and length of the register 137fe8b45aaSThierry Reding region assigned to the VM 138fe8b45aaSThierry Reding - description: physical base address and length of the register 139fe8b45aaSThierry Reding region used by the hypervisor 140fe8b45aaSThierry Reding 141fe8b45aaSThierry Reding resets: 142fe8b45aaSThierry Reding maxItems: 1 143fe8b45aaSThierry Reding 144fe8b45aaSThierry Reding reset-names: 145fe8b45aaSThierry Reding maxItems: 1 146fe8b45aaSThierry Reding 147*ea1a6270SMikko Perttunen iommu-map: 148*ea1a6270SMikko Perttunen description: Specification of stream IDs available for memory context device 149*ea1a6270SMikko Perttunen use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to 150*ea1a6270SMikko Perttunen usable stream IDs. 151*ea1a6270SMikko Perttunen 152fe8b45aaSThierry Reding required: 153fe8b45aaSThierry Reding - reg-names 154fe8b45aaSThierry Reding 155fe8b45aaSThierry Redingexamples: 156fe8b45aaSThierry Reding - | 157fe8b45aaSThierry Reding #include <dt-bindings/clock/tegra20-car.h> 158fe8b45aaSThierry Reding #include <dt-bindings/gpio/tegra-gpio.h> 159fe8b45aaSThierry Reding #include <dt-bindings/memory/tegra20-mc.h> 160fe8b45aaSThierry Reding 161fe8b45aaSThierry Reding host1x@50000000 { 162fe8b45aaSThierry Reding compatible = "nvidia,tegra20-host1x"; 163fe8b45aaSThierry Reding reg = <0x50000000 0x00024000>; 164fe8b45aaSThierry Reding interrupts = <0 65 0x04 /* mpcore syncpt */ 165fe8b45aaSThierry Reding 0 67 0x04>; /* mpcore general */ 166fe8b45aaSThierry Reding interrupt-names = "syncpt", "host1x"; 167fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA20_CLK_HOST1X>; 168fe8b45aaSThierry Reding clock-names = "host1x"; 169fe8b45aaSThierry Reding resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>; 170fe8b45aaSThierry Reding reset-names = "host1x", "mc"; 171fe8b45aaSThierry Reding 172fe8b45aaSThierry Reding #address-cells = <1>; 173fe8b45aaSThierry Reding #size-cells = <1>; 174fe8b45aaSThierry Reding 175fe8b45aaSThierry Reding ranges = <0x54000000 0x54000000 0x04000000>; 176fe8b45aaSThierry Reding 177fe8b45aaSThierry Reding mpe@54040000 { 178fe8b45aaSThierry Reding compatible = "nvidia,tegra20-mpe"; 179fe8b45aaSThierry Reding reg = <0x54040000 0x00040000>; 180fe8b45aaSThierry Reding interrupts = <0 68 0x04>; 181fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA20_CLK_MPE>; 182fe8b45aaSThierry Reding resets = <&tegra_car 60>; 183fe8b45aaSThierry Reding reset-names = "mpe"; 184fe8b45aaSThierry Reding }; 185fe8b45aaSThierry Reding 186fe8b45aaSThierry Reding vi@54080000 { 187fe8b45aaSThierry Reding compatible = "nvidia,tegra20-vi"; 188fe8b45aaSThierry Reding reg = <0x54080000 0x00040000>; 189fe8b45aaSThierry Reding interrupts = <0 69 0x04>; 190fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA20_CLK_VI>; 191fe8b45aaSThierry Reding resets = <&tegra_car 100>; 192fe8b45aaSThierry Reding reset-names = "vi"; 193fe8b45aaSThierry Reding }; 194fe8b45aaSThierry Reding 195fe8b45aaSThierry Reding epp@540c0000 { 196fe8b45aaSThierry Reding compatible = "nvidia,tegra20-epp"; 197fe8b45aaSThierry Reding reg = <0x540c0000 0x00040000>; 198fe8b45aaSThierry Reding interrupts = <0 70 0x04>; 199fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA20_CLK_EPP>; 200fe8b45aaSThierry Reding resets = <&tegra_car 19>; 201fe8b45aaSThierry Reding reset-names = "epp"; 202fe8b45aaSThierry Reding }; 203fe8b45aaSThierry Reding 204fe8b45aaSThierry Reding isp@54100000 { 205fe8b45aaSThierry Reding compatible = "nvidia,tegra20-isp"; 206fe8b45aaSThierry Reding reg = <0x54100000 0x00040000>; 207fe8b45aaSThierry Reding interrupts = <0 71 0x04>; 208fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA20_CLK_ISP>; 209fe8b45aaSThierry Reding resets = <&tegra_car 23>; 210fe8b45aaSThierry Reding reset-names = "isp"; 211fe8b45aaSThierry Reding }; 212fe8b45aaSThierry Reding 213fe8b45aaSThierry Reding gr2d@54140000 { 214fe8b45aaSThierry Reding compatible = "nvidia,tegra20-gr2d"; 215fe8b45aaSThierry Reding reg = <0x54140000 0x00040000>; 216fe8b45aaSThierry Reding interrupts = <0 72 0x04>; 217fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA20_CLK_GR2D>; 218fe8b45aaSThierry Reding resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>; 219fe8b45aaSThierry Reding reset-names = "2d", "mc"; 220fe8b45aaSThierry Reding }; 221fe8b45aaSThierry Reding 222fe8b45aaSThierry Reding gr3d@54180000 { 223fe8b45aaSThierry Reding compatible = "nvidia,tegra20-gr3d"; 224fe8b45aaSThierry Reding reg = <0x54180000 0x00040000>; 225fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA20_CLK_GR3D>; 226fe8b45aaSThierry Reding resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>; 227fe8b45aaSThierry Reding reset-names = "3d", "mc"; 228fe8b45aaSThierry Reding }; 229fe8b45aaSThierry Reding 230fe8b45aaSThierry Reding dc@54200000 { 231fe8b45aaSThierry Reding compatible = "nvidia,tegra20-dc"; 232fe8b45aaSThierry Reding reg = <0x54200000 0x00040000>; 233fe8b45aaSThierry Reding interrupts = <0 73 0x04>; 234fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA20_CLK_DISP1>; 235fe8b45aaSThierry Reding clock-names = "dc"; 236fe8b45aaSThierry Reding resets = <&tegra_car 27>; 237fe8b45aaSThierry Reding reset-names = "dc"; 238fe8b45aaSThierry Reding 239fe8b45aaSThierry Reding rgb { 240fe8b45aaSThierry Reding }; 241fe8b45aaSThierry Reding }; 242fe8b45aaSThierry Reding 243fe8b45aaSThierry Reding dc@54240000 { 244fe8b45aaSThierry Reding compatible = "nvidia,tegra20-dc"; 245fe8b45aaSThierry Reding reg = <0x54240000 0x00040000>; 246fe8b45aaSThierry Reding interrupts = <0 74 0x04>; 247fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA20_CLK_DISP2>; 248fe8b45aaSThierry Reding clock-names = "dc"; 249fe8b45aaSThierry Reding resets = <&tegra_car 26>; 250fe8b45aaSThierry Reding reset-names = "dc"; 251fe8b45aaSThierry Reding 252fe8b45aaSThierry Reding rgb { 253fe8b45aaSThierry Reding }; 254fe8b45aaSThierry Reding }; 255fe8b45aaSThierry Reding 256fe8b45aaSThierry Reding hdmi@54280000 { 257fe8b45aaSThierry Reding compatible = "nvidia,tegra20-hdmi"; 258fe8b45aaSThierry Reding reg = <0x54280000 0x00040000>; 259fe8b45aaSThierry Reding interrupts = <0 75 0x04>; 260fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA20_CLK_HDMI>, 261fe8b45aaSThierry Reding <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 262fe8b45aaSThierry Reding clock-names = "hdmi", "parent"; 263fe8b45aaSThierry Reding resets = <&tegra_car 51>; 264fe8b45aaSThierry Reding reset-names = "hdmi"; 265fe8b45aaSThierry Reding 266fe8b45aaSThierry Reding hdmi-supply = <&vdd_5v0_hdmi>; 267fe8b45aaSThierry Reding pll-supply = <&vdd_hdmi_pll>; 268fe8b45aaSThierry Reding vdd-supply = <&vdd_3v3_hdmi>; 269fe8b45aaSThierry Reding 270fe8b45aaSThierry Reding nvidia,ddc-i2c-bus = <&hdmi_ddc>; 271fe8b45aaSThierry Reding nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 272fe8b45aaSThierry Reding }; 273fe8b45aaSThierry Reding 274fe8b45aaSThierry Reding tvo@542c0000 { 275fe8b45aaSThierry Reding compatible = "nvidia,tegra20-tvo"; 276fe8b45aaSThierry Reding reg = <0x542c0000 0x00040000>; 277fe8b45aaSThierry Reding interrupts = <0 76 0x04>; 278fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA20_CLK_TVO>; 279fe8b45aaSThierry Reding }; 280fe8b45aaSThierry Reding 281fe8b45aaSThierry Reding dsi@54300000 { 282fe8b45aaSThierry Reding compatible = "nvidia,tegra20-dsi"; 283fe8b45aaSThierry Reding reg = <0x54300000 0x00040000>; 284fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA20_CLK_DSI>, 285fe8b45aaSThierry Reding <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 286fe8b45aaSThierry Reding clock-names = "dsi", "parent"; 287fe8b45aaSThierry Reding resets = <&tegra_car 48>; 288fe8b45aaSThierry Reding reset-names = "dsi"; 289fe8b45aaSThierry Reding }; 290fe8b45aaSThierry Reding }; 291fe8b45aaSThierry Reding 292fe8b45aaSThierry Reding - | 293fe8b45aaSThierry Reding #include <dt-bindings/clock/tegra210-car.h> 294fe8b45aaSThierry Reding #include <dt-bindings/interrupt-controller/arm-gic.h> 295fe8b45aaSThierry Reding #include <dt-bindings/memory/tegra210-mc.h> 296fe8b45aaSThierry Reding 297fe8b45aaSThierry Reding host1x@50000000 { 298fe8b45aaSThierry Reding compatible = "nvidia,tegra210-host1x"; 299fe8b45aaSThierry Reding reg = <0x50000000 0x00024000>; 300fe8b45aaSThierry Reding interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* mpcore syncpt */ 301fe8b45aaSThierry Reding <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* mpcore general */ 302fe8b45aaSThierry Reding interrupt-names = "syncpt", "host1x"; 303fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 304fe8b45aaSThierry Reding clock-names = "host1x"; 305fe8b45aaSThierry Reding resets = <&tegra_car 28>; 306fe8b45aaSThierry Reding reset-names = "host1x"; 307fe8b45aaSThierry Reding 308fe8b45aaSThierry Reding #address-cells = <1>; 309fe8b45aaSThierry Reding #size-cells = <1>; 310fe8b45aaSThierry Reding 311fe8b45aaSThierry Reding ranges = <0x54000000 0x54000000 0x01000000>; 312fe8b45aaSThierry Reding iommus = <&mc TEGRA_SWGROUP_HC>; 313fe8b45aaSThierry Reding 314fe8b45aaSThierry Reding vi@54080000 { 315fe8b45aaSThierry Reding compatible = "nvidia,tegra210-vi"; 316fe8b45aaSThierry Reding reg = <0x54080000 0x00000700>; 317fe8b45aaSThierry Reding interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 318fe8b45aaSThierry Reding assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 319fe8b45aaSThierry Reding assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 320fe8b45aaSThierry Reding 321fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA210_CLK_VI>; 322fe8b45aaSThierry Reding power-domains = <&pd_venc>; 323fe8b45aaSThierry Reding 324fe8b45aaSThierry Reding #address-cells = <1>; 325fe8b45aaSThierry Reding #size-cells = <1>; 326fe8b45aaSThierry Reding 327fe8b45aaSThierry Reding ranges = <0x0 0x54080000 0x2000>; 328fe8b45aaSThierry Reding 329fe8b45aaSThierry Reding csi@838 { 330fe8b45aaSThierry Reding compatible = "nvidia,tegra210-csi"; 331fe8b45aaSThierry Reding reg = <0x838 0x1300>; 332fe8b45aaSThierry Reding assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 333fe8b45aaSThierry Reding <&tegra_car TEGRA210_CLK_CILCD>, 334fe8b45aaSThierry Reding <&tegra_car TEGRA210_CLK_CILE>, 335fe8b45aaSThierry Reding <&tegra_car TEGRA210_CLK_CSI_TPG>; 336fe8b45aaSThierry Reding assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 337fe8b45aaSThierry Reding <&tegra_car TEGRA210_CLK_PLL_P>, 338fe8b45aaSThierry Reding <&tegra_car TEGRA210_CLK_PLL_P>; 339fe8b45aaSThierry Reding assigned-clock-rates = <102000000>, 340fe8b45aaSThierry Reding <102000000>, 341fe8b45aaSThierry Reding <102000000>, 342fe8b45aaSThierry Reding <972000000>; 343fe8b45aaSThierry Reding 344fe8b45aaSThierry Reding clocks = <&tegra_car TEGRA210_CLK_CSI>, 345fe8b45aaSThierry Reding <&tegra_car TEGRA210_CLK_CILAB>, 346fe8b45aaSThierry Reding <&tegra_car TEGRA210_CLK_CILCD>, 347fe8b45aaSThierry Reding <&tegra_car TEGRA210_CLK_CILE>, 348fe8b45aaSThierry Reding <&tegra_car TEGRA210_CLK_CSI_TPG>; 349fe8b45aaSThierry Reding clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 350fe8b45aaSThierry Reding power-domains = <&pd_sor>; 351fe8b45aaSThierry Reding }; 352fe8b45aaSThierry Reding }; 353fe8b45aaSThierry Reding }; 354