1*fe8b45aaSThierry Reding# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*fe8b45aaSThierry Reding%YAML 1.2 3*fe8b45aaSThierry Reding--- 4*fe8b45aaSThierry Reding$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml# 5*fe8b45aaSThierry Reding$schema: http://devicetree.org/meta-schemas/core.yaml# 6*fe8b45aaSThierry Reding 7*fe8b45aaSThierry Redingtitle: NVIDIA Tegra186 (and later) Display Controller 8*fe8b45aaSThierry Reding 9*fe8b45aaSThierry Redingmaintainers: 10*fe8b45aaSThierry Reding - Thierry Reding <thierry.reding@gmail.com> 11*fe8b45aaSThierry Reding - Jon Hunter <jonathanh@nvidia.com> 12*fe8b45aaSThierry Reding 13*fe8b45aaSThierry Redingproperties: 14*fe8b45aaSThierry Reding $nodename: 15*fe8b45aaSThierry Reding pattern: "^display@[0-9a-f]+$" 16*fe8b45aaSThierry Reding 17*fe8b45aaSThierry Reding compatible: 18*fe8b45aaSThierry Reding enum: 19*fe8b45aaSThierry Reding - nvidia,tegra186-dc 20*fe8b45aaSThierry Reding - nvidia,tegra194-dc 21*fe8b45aaSThierry Reding 22*fe8b45aaSThierry Reding reg: 23*fe8b45aaSThierry Reding maxItems: 1 24*fe8b45aaSThierry Reding 25*fe8b45aaSThierry Reding interrupts: 26*fe8b45aaSThierry Reding maxItems: 1 27*fe8b45aaSThierry Reding 28*fe8b45aaSThierry Reding clocks: 29*fe8b45aaSThierry Reding items: 30*fe8b45aaSThierry Reding - description: display controller pixel clock 31*fe8b45aaSThierry Reding 32*fe8b45aaSThierry Reding clock-names: 33*fe8b45aaSThierry Reding items: 34*fe8b45aaSThierry Reding - const: dc 35*fe8b45aaSThierry Reding 36*fe8b45aaSThierry Reding resets: 37*fe8b45aaSThierry Reding items: 38*fe8b45aaSThierry Reding - description: display controller reset 39*fe8b45aaSThierry Reding 40*fe8b45aaSThierry Reding reset-names: 41*fe8b45aaSThierry Reding items: 42*fe8b45aaSThierry Reding - const: dc 43*fe8b45aaSThierry Reding 44*fe8b45aaSThierry Reding power-domains: 45*fe8b45aaSThierry Reding maxItems: 1 46*fe8b45aaSThierry Reding 47*fe8b45aaSThierry Reding iommus: 48*fe8b45aaSThierry Reding maxItems: 1 49*fe8b45aaSThierry Reding 50*fe8b45aaSThierry Reding interconnects: 51*fe8b45aaSThierry Reding description: Description of the interconnect paths for the 52*fe8b45aaSThierry Reding display controller; see ../interconnect/interconnect.txt 53*fe8b45aaSThierry Reding for details. 54*fe8b45aaSThierry Reding 55*fe8b45aaSThierry Reding interconnect-names: 56*fe8b45aaSThierry Reding items: 57*fe8b45aaSThierry Reding - const: dma-mem # read-0 58*fe8b45aaSThierry Reding - const: read-1 59*fe8b45aaSThierry Reding 60*fe8b45aaSThierry Reding nvidia,outputs: 61*fe8b45aaSThierry Reding description: A list of phandles of outputs that this display 62*fe8b45aaSThierry Reding controller can drive. 63*fe8b45aaSThierry Reding $ref: "/schemas/types.yaml#/definitions/phandle-array" 64*fe8b45aaSThierry Reding 65*fe8b45aaSThierry Reding nvidia,head: 66*fe8b45aaSThierry Reding description: The number of the display controller head. This 67*fe8b45aaSThierry Reding is used to setup the various types of output to receive 68*fe8b45aaSThierry Reding video data from the given head. 69*fe8b45aaSThierry Reding $ref: "/schemas/types.yaml#/definitions/uint32" 70*fe8b45aaSThierry Reding 71*fe8b45aaSThierry RedingadditionalProperties: false 72*fe8b45aaSThierry Reding 73*fe8b45aaSThierry Redingrequired: 74*fe8b45aaSThierry Reding - compatible 75*fe8b45aaSThierry Reding - reg 76*fe8b45aaSThierry Reding - interrupts 77*fe8b45aaSThierry Reding - clocks 78*fe8b45aaSThierry Reding - clock-names 79*fe8b45aaSThierry Reding - resets 80*fe8b45aaSThierry Reding - reset-names 81*fe8b45aaSThierry Reding - power-domains 82*fe8b45aaSThierry Reding - nvidia,outputs 83*fe8b45aaSThierry Reding - nvidia,head 84*fe8b45aaSThierry Reding 85*fe8b45aaSThierry Reding# see nvidia,tegra186-display.yaml for examples 86