1fe8b45aaSThierry Reding# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2fe8b45aaSThierry Reding%YAML 1.2
3fe8b45aaSThierry Reding---
4fe8b45aaSThierry Reding$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#
5fe8b45aaSThierry Reding$schema: http://devicetree.org/meta-schemas/core.yaml#
6fe8b45aaSThierry Reding
7fe8b45aaSThierry Redingtitle: NVIDIA Tegra186 (and later) Display Controller
8fe8b45aaSThierry Reding
9fe8b45aaSThierry Redingmaintainers:
10fe8b45aaSThierry Reding  - Thierry Reding <thierry.reding@gmail.com>
11fe8b45aaSThierry Reding  - Jon Hunter <jonathanh@nvidia.com>
12fe8b45aaSThierry Reding
13fe8b45aaSThierry Redingproperties:
14fe8b45aaSThierry Reding  $nodename:
15fe8b45aaSThierry Reding    pattern: "^display@[0-9a-f]+$"
16fe8b45aaSThierry Reding
17fe8b45aaSThierry Reding  compatible:
18fe8b45aaSThierry Reding    enum:
19fe8b45aaSThierry Reding      - nvidia,tegra186-dc
20fe8b45aaSThierry Reding      - nvidia,tegra194-dc
21fe8b45aaSThierry Reding
22fe8b45aaSThierry Reding  reg:
23fe8b45aaSThierry Reding    maxItems: 1
24fe8b45aaSThierry Reding
25fe8b45aaSThierry Reding  interrupts:
26fe8b45aaSThierry Reding    maxItems: 1
27fe8b45aaSThierry Reding
28fe8b45aaSThierry Reding  clocks:
29fe8b45aaSThierry Reding    items:
30fe8b45aaSThierry Reding      - description: display controller pixel clock
31fe8b45aaSThierry Reding
32fe8b45aaSThierry Reding  clock-names:
33fe8b45aaSThierry Reding    items:
34fe8b45aaSThierry Reding      - const: dc
35fe8b45aaSThierry Reding
36fe8b45aaSThierry Reding  resets:
37fe8b45aaSThierry Reding    items:
38fe8b45aaSThierry Reding      - description: display controller reset
39fe8b45aaSThierry Reding
40fe8b45aaSThierry Reding  reset-names:
41fe8b45aaSThierry Reding    items:
42fe8b45aaSThierry Reding      - const: dc
43fe8b45aaSThierry Reding
44fe8b45aaSThierry Reding  power-domains:
45fe8b45aaSThierry Reding    maxItems: 1
46fe8b45aaSThierry Reding
47fe8b45aaSThierry Reding  iommus:
48fe8b45aaSThierry Reding    maxItems: 1
49fe8b45aaSThierry Reding
50fe8b45aaSThierry Reding  interconnects:
51fe8b45aaSThierry Reding    description: Description of the interconnect paths for the
52fe8b45aaSThierry Reding      display controller; see ../interconnect/interconnect.txt
53fe8b45aaSThierry Reding      for details.
54fe8b45aaSThierry Reding
55fe8b45aaSThierry Reding  interconnect-names:
56fe8b45aaSThierry Reding    items:
57fe8b45aaSThierry Reding      - const: dma-mem # read-0
58fe8b45aaSThierry Reding      - const: read-1
59fe8b45aaSThierry Reding
60fe8b45aaSThierry Reding  nvidia,outputs:
61fe8b45aaSThierry Reding    description: A list of phandles of outputs that this display
62fe8b45aaSThierry Reding      controller can drive.
63*4334aec0SRob Herring    $ref: /schemas/types.yaml#/definitions/phandle-array
64fe8b45aaSThierry Reding
65fe8b45aaSThierry Reding  nvidia,head:
66fe8b45aaSThierry Reding    description: The number of the display controller head. This
67fe8b45aaSThierry Reding      is used to setup the various types of output to receive
68fe8b45aaSThierry Reding      video data from the given head.
69*4334aec0SRob Herring    $ref: /schemas/types.yaml#/definitions/uint32
70fe8b45aaSThierry Reding
71fe8b45aaSThierry RedingadditionalProperties: false
72fe8b45aaSThierry Reding
73fe8b45aaSThierry Redingrequired:
74fe8b45aaSThierry Reding  - compatible
75fe8b45aaSThierry Reding  - reg
76fe8b45aaSThierry Reding  - interrupts
77fe8b45aaSThierry Reding  - clocks
78fe8b45aaSThierry Reding  - clock-names
79fe8b45aaSThierry Reding  - resets
80fe8b45aaSThierry Reding  - reset-names
81fe8b45aaSThierry Reding  - power-domains
82fe8b45aaSThierry Reding  - nvidia,outputs
83fe8b45aaSThierry Reding  - nvidia,head
84fe8b45aaSThierry Reding
85fe8b45aaSThierry Reding# see nvidia,tegra186-display.yaml for examples
86