1*2abb0b99SLinus Walleij# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2*2abb0b99SLinus Walleij%YAML 1.2
3*2abb0b99SLinus Walleij---
4*2abb0b99SLinus Walleij$id: http://devicetree.org/schemas/display/ste,mcde.yaml#
5*2abb0b99SLinus Walleij$schema: http://devicetree.org/meta-schemas/core.yaml#
6*2abb0b99SLinus Walleij
7*2abb0b99SLinus Walleijtitle: ST-Ericsson Multi Channel Display Engine MCDE
8*2abb0b99SLinus Walleij
9*2abb0b99SLinus Walleijmaintainers:
10*2abb0b99SLinus Walleij  - Linus Walleij <linus.walleij@linaro.org>
11*2abb0b99SLinus Walleij
12*2abb0b99SLinus Walleijproperties:
13*2abb0b99SLinus Walleij  compatible:
14*2abb0b99SLinus Walleij    const: ste,mcde
15*2abb0b99SLinus Walleij
16*2abb0b99SLinus Walleij  reg:
17*2abb0b99SLinus Walleij    maxItems: 1
18*2abb0b99SLinus Walleij
19*2abb0b99SLinus Walleij  interrupts:
20*2abb0b99SLinus Walleij    maxItems: 1
21*2abb0b99SLinus Walleij
22*2abb0b99SLinus Walleij  clocks:
23*2abb0b99SLinus Walleij    description: an array of the MCDE clocks
24*2abb0b99SLinus Walleij    items:
25*2abb0b99SLinus Walleij      - description: MCDECLK (main MCDE clock)
26*2abb0b99SLinus Walleij      - description: LCDCLK (LCD clock)
27*2abb0b99SLinus Walleij      - description: PLLDSI (HDMI clock)
28*2abb0b99SLinus Walleij
29*2abb0b99SLinus Walleij  clock-names:
30*2abb0b99SLinus Walleij    items:
31*2abb0b99SLinus Walleij      - const: mcde
32*2abb0b99SLinus Walleij      - const: lcd
33*2abb0b99SLinus Walleij      - const: hdmi
34*2abb0b99SLinus Walleij
35*2abb0b99SLinus Walleij  resets:
36*2abb0b99SLinus Walleij    maxItems: 1
37*2abb0b99SLinus Walleij
38*2abb0b99SLinus Walleij  epod-supply:
39*2abb0b99SLinus Walleij    description: a phandle to the EPOD regulator
40*2abb0b99SLinus Walleij
41*2abb0b99SLinus Walleij  vana-supply:
42*2abb0b99SLinus Walleij    description: a phandle to the analog voltage regulator
43*2abb0b99SLinus Walleij
44*2abb0b99SLinus Walleij  port:
45*2abb0b99SLinus Walleij    type: object
46*2abb0b99SLinus Walleij    description:
47*2abb0b99SLinus Walleij      A DPI port node with endpoint definitions as defined in
48*2abb0b99SLinus Walleij      Documentation/devicetree/bindings/media/video-interfaces.txt
49*2abb0b99SLinus Walleij
50*2abb0b99SLinus Walleij  "#address-cells":
51*2abb0b99SLinus Walleij    const: 1
52*2abb0b99SLinus Walleij
53*2abb0b99SLinus Walleij  "#size-cells":
54*2abb0b99SLinus Walleij    const: 1
55*2abb0b99SLinus Walleij
56*2abb0b99SLinus Walleij  ranges: true
57*2abb0b99SLinus Walleij
58*2abb0b99SLinus WalleijpatternProperties:
59*2abb0b99SLinus Walleij  "^dsi@[0-9a-f]+$":
60*2abb0b99SLinus Walleij    description: subnodes for the three DSI host adapters
61*2abb0b99SLinus Walleij    type: object
62*2abb0b99SLinus Walleij    allOf:
63*2abb0b99SLinus Walleij      - $ref: dsi-controller.yaml#
64*2abb0b99SLinus Walleij    properties:
65*2abb0b99SLinus Walleij      compatible:
66*2abb0b99SLinus Walleij        const: ste,mcde-dsi
67*2abb0b99SLinus Walleij
68*2abb0b99SLinus Walleij      reg:
69*2abb0b99SLinus Walleij        maxItems: 1
70*2abb0b99SLinus Walleij
71*2abb0b99SLinus Walleij      vana-supply:
72*2abb0b99SLinus Walleij        description: a phandle to the analog voltage regulator
73*2abb0b99SLinus Walleij
74*2abb0b99SLinus Walleij      clocks:
75*2abb0b99SLinus Walleij        description: phandles to the high speed and low power (energy save) clocks
76*2abb0b99SLinus Walleij          the high speed clock is not present on the third (dsi2) block, so it
77*2abb0b99SLinus Walleij          should only have the "lp" clock
78*2abb0b99SLinus Walleij        minItems: 1
79*2abb0b99SLinus Walleij        maxItems: 2
80*2abb0b99SLinus Walleij
81*2abb0b99SLinus Walleij      clock-names:
82*2abb0b99SLinus Walleij        oneOf:
83*2abb0b99SLinus Walleij          - items:
84*2abb0b99SLinus Walleij              - const: hs
85*2abb0b99SLinus Walleij              - const: lp
86*2abb0b99SLinus Walleij          - items:
87*2abb0b99SLinus Walleij              - const: lp
88*2abb0b99SLinus Walleij
89*2abb0b99SLinus Walleij    required:
90*2abb0b99SLinus Walleij      - compatible
91*2abb0b99SLinus Walleij      - reg
92*2abb0b99SLinus Walleij      - vana-supply
93*2abb0b99SLinus Walleij      - clocks
94*2abb0b99SLinus Walleij      - clock-names
95*2abb0b99SLinus Walleij
96*2abb0b99SLinus Walleij    unevaluatedProperties: false
97*2abb0b99SLinus Walleij
98*2abb0b99SLinus Walleijrequired:
99*2abb0b99SLinus Walleij  - compatible
100*2abb0b99SLinus Walleij  - reg
101*2abb0b99SLinus Walleij  - interrupts
102*2abb0b99SLinus Walleij  - clocks
103*2abb0b99SLinus Walleij  - clock-names
104*2abb0b99SLinus Walleij  - epod-supply
105*2abb0b99SLinus Walleij  - vana-supply
106*2abb0b99SLinus Walleij
107*2abb0b99SLinus WalleijadditionalProperties: false
108*2abb0b99SLinus Walleij
109*2abb0b99SLinus Walleijexamples:
110*2abb0b99SLinus Walleij  - |
111*2abb0b99SLinus Walleij    #include <dt-bindings/interrupt-controller/irq.h>
112*2abb0b99SLinus Walleij    #include <dt-bindings/interrupt-controller/arm-gic.h>
113*2abb0b99SLinus Walleij    #include <dt-bindings/mfd/dbx500-prcmu.h>
114*2abb0b99SLinus Walleij    #include <dt-bindings/gpio/gpio.h>
115*2abb0b99SLinus Walleij
116*2abb0b99SLinus Walleij    mcde@a0350000 {
117*2abb0b99SLinus Walleij      compatible = "ste,mcde";
118*2abb0b99SLinus Walleij      reg = <0xa0350000 0x1000>;
119*2abb0b99SLinus Walleij      interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
120*2abb0b99SLinus Walleij      epod-supply = <&db8500_b2r2_mcde_reg>;
121*2abb0b99SLinus Walleij      vana-supply = <&ab8500_ldo_ana_reg>;
122*2abb0b99SLinus Walleij      clocks = <&prcmu_clk PRCMU_MCDECLK>,
123*2abb0b99SLinus Walleij               <&prcmu_clk PRCMU_LCDCLK>,
124*2abb0b99SLinus Walleij               <&prcmu_clk PRCMU_PLLDSI>;
125*2abb0b99SLinus Walleij      clock-names = "mcde", "lcd", "hdmi";
126*2abb0b99SLinus Walleij      #address-cells = <1>;
127*2abb0b99SLinus Walleij      #size-cells = <1>;
128*2abb0b99SLinus Walleij      ranges;
129*2abb0b99SLinus Walleij
130*2abb0b99SLinus Walleij      dsi0: dsi@a0351000 {
131*2abb0b99SLinus Walleij        compatible = "ste,mcde-dsi";
132*2abb0b99SLinus Walleij        reg = <0xa0351000 0x1000>;
133*2abb0b99SLinus Walleij        vana-supply = <&ab8500_ldo_ana_reg>;
134*2abb0b99SLinus Walleij        clocks = <&prcmu_clk PRCMU_DSI0CLK>, <&prcmu_clk PRCMU_DSI0ESCCLK>;
135*2abb0b99SLinus Walleij        clock-names = "hs", "lp";
136*2abb0b99SLinus Walleij        #address-cells = <1>;
137*2abb0b99SLinus Walleij        #size-cells = <0>;
138*2abb0b99SLinus Walleij
139*2abb0b99SLinus Walleij        panel@0 {
140*2abb0b99SLinus Walleij          compatible = "samsung,s6d16d0";
141*2abb0b99SLinus Walleij          reg = <0>;
142*2abb0b99SLinus Walleij          vdd1-supply = <&ab8500_ldo_aux1_reg>;
143*2abb0b99SLinus Walleij          reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
144*2abb0b99SLinus Walleij        };
145*2abb0b99SLinus Walleij      };
146*2abb0b99SLinus Walleij
147*2abb0b99SLinus Walleij      dsi1: dsi@a0352000 {
148*2abb0b99SLinus Walleij        compatible = "ste,mcde-dsi";
149*2abb0b99SLinus Walleij        reg = <0xa0352000 0x1000>;
150*2abb0b99SLinus Walleij        vana-supply = <&ab8500_ldo_ana_reg>;
151*2abb0b99SLinus Walleij        clocks = <&prcmu_clk PRCMU_DSI1CLK>, <&prcmu_clk PRCMU_DSI1ESCCLK>;
152*2abb0b99SLinus Walleij        clock-names = "hs", "lp";
153*2abb0b99SLinus Walleij        #address-cells = <1>;
154*2abb0b99SLinus Walleij        #size-cells = <0>;
155*2abb0b99SLinus Walleij      };
156*2abb0b99SLinus Walleij
157*2abb0b99SLinus Walleij      dsi2: dsi@a0353000 {
158*2abb0b99SLinus Walleij        compatible = "ste,mcde-dsi";
159*2abb0b99SLinus Walleij        reg = <0xa0353000 0x1000>;
160*2abb0b99SLinus Walleij        vana-supply = <&ab8500_ldo_ana_reg>;
161*2abb0b99SLinus Walleij        /* This DSI port only has the Low Power / Energy Save clock */
162*2abb0b99SLinus Walleij        clocks = <&prcmu_clk PRCMU_DSI2ESCCLK>;
163*2abb0b99SLinus Walleij        clock-names = "lp";
164*2abb0b99SLinus Walleij        #address-cells = <1>;
165*2abb0b99SLinus Walleij        #size-cells = <0>;
166*2abb0b99SLinus Walleij      };
167*2abb0b99SLinus Walleij    };
168*2abb0b99SLinus Walleij
169*2abb0b99SLinus Walleij...
170