1*8cae15c6SKevin Tang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*8cae15c6SKevin Tang%YAML 1.2
3*8cae15c6SKevin Tang---
4*8cae15c6SKevin Tang$id: http://devicetree.org/schemas/display/sprd/sprd,sharkl3-dpu.yaml#
5*8cae15c6SKevin Tang$schema: http://devicetree.org/meta-schemas/core.yaml#
6*8cae15c6SKevin Tang
7*8cae15c6SKevin Tangtitle: Unisoc Sharkl3 Display Processor Unit (DPU)
8*8cae15c6SKevin Tang
9*8cae15c6SKevin Tangmaintainers:
10*8cae15c6SKevin Tang  - Kevin Tang <kevin.tang@unisoc.com>
11*8cae15c6SKevin Tang
12*8cae15c6SKevin Tangdescription: |
13*8cae15c6SKevin Tang  DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs
14*8cae15c6SKevin Tang  which transfers the image data from a video memory buffer to an internal
15*8cae15c6SKevin Tang  LCD interface.
16*8cae15c6SKevin Tang
17*8cae15c6SKevin Tangproperties:
18*8cae15c6SKevin Tang  compatible:
19*8cae15c6SKevin Tang    const: sprd,sharkl3-dpu
20*8cae15c6SKevin Tang
21*8cae15c6SKevin Tang  reg:
22*8cae15c6SKevin Tang    maxItems: 1
23*8cae15c6SKevin Tang
24*8cae15c6SKevin Tang  interrupts:
25*8cae15c6SKevin Tang    maxItems: 1
26*8cae15c6SKevin Tang
27*8cae15c6SKevin Tang  clocks:
28*8cae15c6SKevin Tang    minItems: 2
29*8cae15c6SKevin Tang
30*8cae15c6SKevin Tang  clock-names:
31*8cae15c6SKevin Tang    items:
32*8cae15c6SKevin Tang      - const: clk_src_128m
33*8cae15c6SKevin Tang      - const: clk_src_384m
34*8cae15c6SKevin Tang
35*8cae15c6SKevin Tang  power-domains:
36*8cae15c6SKevin Tang    maxItems: 1
37*8cae15c6SKevin Tang
38*8cae15c6SKevin Tang  iommus:
39*8cae15c6SKevin Tang    maxItems: 1
40*8cae15c6SKevin Tang
41*8cae15c6SKevin Tang  port:
42*8cae15c6SKevin Tang    type: object
43*8cae15c6SKevin Tang    description:
44*8cae15c6SKevin Tang      A port node with endpoint definitions as defined in
45*8cae15c6SKevin Tang      Documentation/devicetree/bindings/media/video-interfaces.txt.
46*8cae15c6SKevin Tang      That port should be the output endpoint, usually output to
47*8cae15c6SKevin Tang      the associated DSI.
48*8cae15c6SKevin Tang
49*8cae15c6SKevin Tangrequired:
50*8cae15c6SKevin Tang  - compatible
51*8cae15c6SKevin Tang  - reg
52*8cae15c6SKevin Tang  - interrupts
53*8cae15c6SKevin Tang  - clocks
54*8cae15c6SKevin Tang  - clock-names
55*8cae15c6SKevin Tang  - port
56*8cae15c6SKevin Tang
57*8cae15c6SKevin TangadditionalProperties: false
58*8cae15c6SKevin Tang
59*8cae15c6SKevin Tangexamples:
60*8cae15c6SKevin Tang  - |
61*8cae15c6SKevin Tang    #include <dt-bindings/interrupt-controller/arm-gic.h>
62*8cae15c6SKevin Tang    #include <dt-bindings/clock/sprd,sc9860-clk.h>
63*8cae15c6SKevin Tang    dpu: dpu@63000000 {
64*8cae15c6SKevin Tang        compatible = "sprd,sharkl3-dpu";
65*8cae15c6SKevin Tang        reg = <0x63000000 0x1000>;
66*8cae15c6SKevin Tang        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
67*8cae15c6SKevin Tang        clock-names = "clk_src_128m", "clk_src_384m";
68*8cae15c6SKevin Tang
69*8cae15c6SKevin Tang        clocks = <&pll CLK_TWPLL_128M>,
70*8cae15c6SKevin Tang          <&pll CLK_TWPLL_384M>;
71*8cae15c6SKevin Tang
72*8cae15c6SKevin Tang        dpu_port: port {
73*8cae15c6SKevin Tang            dpu_out: endpoint {
74*8cae15c6SKevin Tang                remote-endpoint = <&dsi_in>;
75*8cae15c6SKevin Tang            };
76*8cae15c6SKevin Tang        };
77*8cae15c6SKevin Tang    };
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