1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8450 Display MDSS
8
9maintainers:
10  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11
12description:
13  SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14  DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm8450-mdss
21
22  clocks:
23    items:
24      - description: Display AHB
25      - description: Display hf AXI
26      - description: Display sf AXI
27      - description: Display core
28
29  iommus:
30    maxItems: 1
31
32  interconnects:
33    maxItems: 2
34
35  interconnect-names:
36    maxItems: 2
37
38patternProperties:
39  "^display-controller@[0-9a-f]+$":
40    type: object
41    properties:
42      compatible:
43        const: qcom,sm8450-dpu
44
45  "^displayport-controller@[0-9a-f]+$":
46    type: object
47    properties:
48      compatible:
49        items:
50          - const: qcom,sm8450-dp
51          - const: qcom,sm8350-dp
52
53  "^dsi@[0-9a-f]+$":
54    type: object
55    properties:
56      compatible:
57        items:
58          - const: qcom,sm8450-dsi-ctrl
59          - const: qcom,mdss-dsi-ctrl
60
61  "^phy@[0-9a-f]+$":
62    type: object
63    properties:
64      compatible:
65        const: qcom,sm8450-dsi-phy-5nm
66
67required:
68  - compatible
69
70unevaluatedProperties: false
71
72examples:
73  - |
74    #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
75    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
76    #include <dt-bindings/clock/qcom,rpmh.h>
77    #include <dt-bindings/interrupt-controller/arm-gic.h>
78    #include <dt-bindings/interconnect/qcom,sm8450.h>
79    #include <dt-bindings/power/qcom,rpmhpd.h>
80
81    display-subsystem@ae00000 {
82        compatible = "qcom,sm8450-mdss";
83        reg = <0x0ae00000 0x1000>;
84        reg-names = "mdss";
85
86        interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
87                        <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>;
88        interconnect-names = "mdp0-mem", "mdp1-mem";
89
90        resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
91
92        power-domains = <&dispcc MDSS_GDSC>;
93
94        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
95                 <&gcc GCC_DISP_HF_AXI_CLK>,
96                 <&gcc GCC_DISP_SF_AXI_CLK>,
97                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
98        clock-names = "iface", "bus", "nrt_bus", "core";
99
100        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
101        interrupt-controller;
102        #interrupt-cells = <1>;
103
104        iommus = <&apps_smmu 0x2800 0x402>;
105
106        #address-cells = <1>;
107        #size-cells = <1>;
108        ranges;
109
110        display-controller@ae01000 {
111            compatible = "qcom,sm8450-dpu";
112            reg = <0x0ae01000 0x8f000>,
113                  <0x0aeb0000 0x2008>;
114            reg-names = "mdp", "vbif";
115
116            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
117                    <&gcc GCC_DISP_SF_AXI_CLK>,
118                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
119                    <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
120                    <&dispcc DISP_CC_MDSS_MDP_CLK>,
121                    <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
122            clock-names = "bus",
123                          "nrt_bus",
124                          "iface",
125                          "lut",
126                          "core",
127                          "vsync";
128
129            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
130            assigned-clock-rates = <19200000>;
131
132            operating-points-v2 = <&mdp_opp_table>;
133            power-domains = <&rpmhpd RPMHPD_MMCX>;
134
135            interrupt-parent = <&mdss>;
136            interrupts = <0>;
137
138            ports {
139                #address-cells = <1>;
140                #size-cells = <0>;
141
142                port@0 {
143                    reg = <0>;
144                    dpu_intf1_out: endpoint {
145                        remote-endpoint = <&dsi0_in>;
146                    };
147                };
148
149                port@1 {
150                    reg = <1>;
151                    dpu_intf2_out: endpoint {
152                        remote-endpoint = <&dsi1_in>;
153                    };
154                };
155            };
156
157            mdp_opp_table: opp-table {
158                compatible = "operating-points-v2";
159
160                opp-172000000{
161                    opp-hz = /bits/ 64 <172000000>;
162                    required-opps = <&rpmhpd_opp_low_svs_d1>;
163                };
164
165                opp-200000000 {
166                    opp-hz = /bits/ 64 <200000000>;
167                    required-opps = <&rpmhpd_opp_low_svs>;
168                };
169
170                opp-325000000 {
171                    opp-hz = /bits/ 64 <325000000>;
172                    required-opps = <&rpmhpd_opp_svs>;
173                };
174
175                opp-375000000 {
176                    opp-hz = /bits/ 64 <375000000>;
177                    required-opps = <&rpmhpd_opp_svs_l1>;
178                };
179
180                opp-500000000 {
181                    opp-hz = /bits/ 64 <500000000>;
182                    required-opps = <&rpmhpd_opp_nom>;
183                };
184            };
185        };
186
187        dsi@ae94000 {
188            compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
189            reg = <0x0ae94000 0x400>;
190            reg-names = "dsi_ctrl";
191
192            interrupt-parent = <&mdss>;
193            interrupts = <4>;
194
195            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
196                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
197                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
198                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
199                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
200                     <&gcc GCC_DISP_HF_AXI_CLK>;
201            clock-names = "byte",
202                          "byte_intf",
203                          "pixel",
204                          "core",
205                          "iface",
206                          "bus";
207
208            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
209                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
210            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
211
212            operating-points-v2 = <&dsi_opp_table>;
213            power-domains = <&rpmhpd RPMHPD_MMCX>;
214
215            phys = <&dsi0_phy>;
216            phy-names = "dsi";
217
218            #address-cells = <1>;
219            #size-cells = <0>;
220
221            ports {
222                #address-cells = <1>;
223                #size-cells = <0>;
224
225                port@0 {
226                    reg = <0>;
227                    dsi0_in: endpoint {
228                        remote-endpoint = <&dpu_intf1_out>;
229                    };
230                };
231
232                port@1 {
233                    reg = <1>;
234                    dsi0_out: endpoint {
235                    };
236                };
237            };
238
239            dsi_opp_table: opp-table {
240                compatible = "operating-points-v2";
241
242                opp-160310000{
243                    opp-hz = /bits/ 64 <160310000>;
244                    required-opps = <&rpmhpd_opp_low_svs_d1>;
245                };
246
247                opp-187500000 {
248                    opp-hz = /bits/ 64 <187500000>;
249                    required-opps = <&rpmhpd_opp_low_svs>;
250                };
251
252                opp-300000000 {
253                    opp-hz = /bits/ 64 <300000000>;
254                    required-opps = <&rpmhpd_opp_svs>;
255                };
256
257                opp-358000000 {
258                    opp-hz = /bits/ 64 <358000000>;
259                    required-opps = <&rpmhpd_opp_svs_l1>;
260                };
261            };
262        };
263
264        dsi0_phy: phy@ae94400 {
265            compatible = "qcom,sm8450-dsi-phy-5nm";
266            reg = <0x0ae94400 0x200>,
267                  <0x0ae94600 0x280>,
268                  <0x0ae94900 0x260>;
269            reg-names = "dsi_phy",
270                        "dsi_phy_lane",
271                        "dsi_pll";
272
273            #clock-cells = <1>;
274            #phy-cells = <0>;
275
276            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
277                     <&rpmhcc RPMH_CXO_CLK>;
278            clock-names = "iface", "ref";
279            vdds-supply = <&vreg_dsi_phy>;
280        };
281
282        dsi@ae96000 {
283            compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
284            reg = <0x0ae96000 0x400>;
285            reg-names = "dsi_ctrl";
286
287            interrupt-parent = <&mdss>;
288            interrupts = <5>;
289
290            clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
291                     <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
292                     <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
293                     <&dispcc DISP_CC_MDSS_ESC1_CLK>,
294                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
295                     <&gcc GCC_DISP_HF_AXI_CLK>;
296            clock-names = "byte",
297                          "byte_intf",
298                          "pixel",
299                          "core",
300                          "iface",
301                          "bus";
302
303            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
304                              <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
305            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
306
307            operating-points-v2 = <&dsi_opp_table>;
308            power-domains = <&rpmhpd RPMHPD_MMCX>;
309
310            phys = <&dsi1_phy>;
311            phy-names = "dsi";
312
313            #address-cells = <1>;
314            #size-cells = <0>;
315
316            ports {
317                #address-cells = <1>;
318                #size-cells = <0>;
319
320                port@0 {
321                    reg = <0>;
322                    dsi1_in: endpoint {
323                        remote-endpoint = <&dpu_intf2_out>;
324                    };
325                };
326
327                port@1 {
328                    reg = <1>;
329                    dsi1_out: endpoint {
330                    };
331                };
332            };
333        };
334
335        dsi1_phy: phy@ae96400 {
336            compatible = "qcom,sm8450-dsi-phy-5nm";
337            reg = <0x0ae96400 0x200>,
338                  <0x0ae96600 0x280>,
339                  <0x0ae96900 0x260>;
340            reg-names = "dsi_phy",
341                        "dsi_phy_lane",
342                        "dsi_pll";
343
344            #clock-cells = <1>;
345            #phy-cells = <0>;
346
347            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
348                     <&rpmhcc RPMH_CXO_CLK>;
349            clock-names = "iface", "ref";
350            vdds-supply = <&vreg_dsi_phy>;
351        };
352    };
353...
354