1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM8350 Display MDSS
8
9maintainers:
10  - Robert Foss <robert.foss@linaro.org>
11
12description:
13  MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like
14  DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    items:
21      - const: qcom,sm8350-mdss
22
23  clocks:
24    items:
25      - description: Display AHB clock from gcc
26      - description: Display hf axi clock
27      - description: Display sf axi clock
28      - description: Display core clock
29
30  clock-names:
31    items:
32      - const: iface
33      - const: bus
34      - const: nrt_bus
35      - const: core
36
37  iommus:
38    maxItems: 1
39
40  interconnects:
41    maxItems: 2
42
43  interconnect-names:
44    items:
45      - const: mdp0-mem
46      - const: mdp1-mem
47
48patternProperties:
49  "^display-controller@[0-9a-f]+$":
50    type: object
51    properties:
52      compatible:
53        const: qcom,sm8350-dpu
54
55  "^displayport-controller@[0-9a-f]+$":
56    type: object
57    properties:
58      compatible:
59        const: qcom,sm8350-dp
60
61  "^dsi@[0-9a-f]+$":
62    type: object
63    properties:
64      compatible:
65        items:
66          - const: qcom,sm8350-dsi-ctrl
67          - const: qcom,mdss-dsi-ctrl
68
69  "^phy@[0-9a-f]+$":
70    type: object
71    properties:
72      compatible:
73        const: qcom,sm8350-dsi-phy-5nm
74
75unevaluatedProperties: false
76
77examples:
78  - |
79    #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
80    #include <dt-bindings/clock/qcom,gcc-sm8350.h>
81    #include <dt-bindings/clock/qcom,rpmh.h>
82    #include <dt-bindings/interrupt-controller/arm-gic.h>
83    #include <dt-bindings/interconnect/qcom,sm8350.h>
84    #include <dt-bindings/power/qcom,rpmhpd.h>
85
86    display-subsystem@ae00000 {
87        compatible = "qcom,sm8350-mdss";
88        reg = <0x0ae00000 0x1000>;
89        reg-names = "mdss";
90
91        interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
92                        <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
93        interconnect-names = "mdp0-mem", "mdp1-mem";
94
95        power-domains = <&dispcc MDSS_GDSC>;
96        resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
97
98        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
99                 <&gcc GCC_DISP_HF_AXI_CLK>,
100                 <&gcc GCC_DISP_SF_AXI_CLK>,
101                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
102        clock-names = "iface", "bus", "nrt_bus", "core";
103
104        iommus = <&apps_smmu 0x820 0x402>;
105
106        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
107        interrupt-controller;
108        #interrupt-cells = <1>;
109
110        #address-cells = <1>;
111        #size-cells = <1>;
112        ranges;
113
114        display-controller@ae01000 {
115            compatible = "qcom,sm8350-dpu";
116            reg = <0x0ae01000 0x8f000>,
117                  <0x0aeb0000 0x2008>;
118            reg-names = "mdp", "vbif";
119
120            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
121                     <&gcc GCC_DISP_SF_AXI_CLK>,
122                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
123                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
124                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
125                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
126            clock-names = "bus",
127                          "nrt_bus",
128                          "iface",
129                          "lut",
130                          "core",
131                          "vsync";
132
133            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
134            assigned-clock-rates = <19200000>;
135
136            operating-points-v2 = <&mdp_opp_table>;
137            power-domains = <&rpmhpd RPMHPD_MMCX>;
138
139            interrupt-parent = <&mdss>;
140            interrupts = <0>;
141
142            ports {
143                #address-cells = <1>;
144                #size-cells = <0>;
145
146                port@0 {
147                    reg = <0>;
148                    dpu_intf1_out: endpoint {
149                        remote-endpoint = <&dsi0_in>;
150                    };
151                };
152            };
153
154            mdp_opp_table: opp-table {
155                compatible = "operating-points-v2";
156
157                opp-200000000 {
158                    opp-hz = /bits/ 64 <200000000>;
159                    required-opps = <&rpmhpd_opp_low_svs>;
160                };
161
162                opp-300000000 {
163                    opp-hz = /bits/ 64 <300000000>;
164                    required-opps = <&rpmhpd_opp_svs>;
165                };
166
167                opp-345000000 {
168                    opp-hz = /bits/ 64 <345000000>;
169                    required-opps = <&rpmhpd_opp_svs_l1>;
170                };
171
172                opp-460000000 {
173                    opp-hz = /bits/ 64 <460000000>;
174                    required-opps = <&rpmhpd_opp_nom>;
175                };
176            };
177        };
178
179        dsi0: dsi@ae94000 {
180            compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
181            reg = <0x0ae94000 0x400>;
182            reg-names = "dsi_ctrl";
183
184            interrupt-parent = <&mdss>;
185            interrupts = <4>;
186
187            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
188                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
189                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
190                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
191                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
192                     <&gcc GCC_DISP_HF_AXI_CLK>;
193            clock-names = "byte",
194                      "byte_intf",
195                      "pixel",
196                      "core",
197                      "iface",
198                      "bus";
199
200            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
201                          <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
202            assigned-clock-parents = <&mdss_dsi0_phy 0>,
203                                 <&mdss_dsi0_phy 1>;
204
205            operating-points-v2 = <&dsi_opp_table>;
206            power-domains = <&rpmhpd RPMHPD_MMCX>;
207
208            phys = <&mdss_dsi0_phy>;
209
210            ports {
211             #address-cells = <1>;
212                #size-cells = <0>;
213
214                port@0 {
215                    reg = <0>;
216                    dsi0_in: endpoint {
217                        remote-endpoint = <&dpu_intf1_out>;
218                    };
219                };
220
221                port@1 {
222                    reg = <1>;
223                    dsi0_out: endpoint {
224                    };
225                };
226            };
227        };
228    };
229...
230