1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm6125-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM6125 Display MDSS
8
9maintainers:
10  - Marijn Suijten <marijn.suijten@somainline.org>
11
12description:
13  SM6125 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14  like DPU display controller, DSI and DP interfaces etc.
15
16$ref: /schemas/display/msm/mdss-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm6125-mdss
21
22  clocks:
23    items:
24      - description: Display AHB clock from gcc
25      - description: Display AHB clock
26      - description: Display core clock
27
28  clock-names:
29    items:
30      - const: iface
31      - const: ahb
32      - const: core
33
34  iommus:
35    maxItems: 1
36
37  interconnects:
38    maxItems: 2
39
40  interconnect-names:
41    maxItems: 2
42
43patternProperties:
44  "^display-controller@[0-9a-f]+$":
45    type: object
46    properties:
47      compatible:
48        const: qcom,sm6125-dpu
49
50  "^dsi@[0-9a-f]+$":
51    type: object
52    properties:
53      compatible:
54        items:
55          - const: qcom,sm6125-dsi-ctrl
56          - const: qcom,mdss-dsi-ctrl
57
58  "^phy@[0-9a-f]+$":
59    type: object
60    properties:
61      compatible:
62        const: qcom,sm6125-dsi-phy-14nm
63
64unevaluatedProperties: false
65
66examples:
67  - |
68    #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
69    #include <dt-bindings/clock/qcom,gcc-sm6125.h>
70    #include <dt-bindings/clock/qcom,rpmcc.h>
71    #include <dt-bindings/interrupt-controller/arm-gic.h>
72    #include <dt-bindings/power/qcom-rpmpd.h>
73
74    display-subsystem@5e00000 {
75        compatible = "qcom,sm6125-mdss";
76        reg = <0x05e00000 0x1000>;
77        reg-names = "mdss";
78
79        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
80        interrupt-controller;
81        #interrupt-cells = <1>;
82
83        clocks = <&gcc GCC_DISP_AHB_CLK>,
84                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
85                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
86        clock-names = "iface",
87                      "ahb",
88                      "core";
89
90        power-domains = <&dispcc MDSS_GDSC>;
91
92        iommus = <&apps_smmu 0x400 0x0>;
93
94        #address-cells = <1>;
95        #size-cells = <1>;
96        ranges;
97
98        display-controller@5e01000 {
99            compatible = "qcom,sm6125-dpu";
100            reg = <0x05e01000 0x83208>,
101                  <0x05eb0000 0x2008>;
102            reg-names = "mdp", "vbif";
103
104            interrupt-parent = <&mdss>;
105            interrupts = <0>;
106
107            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
108                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
109                     <&dispcc DISP_CC_MDSS_ROT_CLK>,
110                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
111                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
112                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
113                     <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
114            clock-names = "bus",
115                          "iface",
116                          "rot",
117                          "lut",
118                          "core",
119                          "vsync",
120                          "throttle";
121            assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
122            assigned-clock-rates = <19200000>;
123
124            operating-points-v2 = <&mdp_opp_table>;
125            power-domains = <&rpmpd SM6125_VDDCX>;
126
127            ports {
128                #address-cells = <1>;
129                #size-cells = <0>;
130
131                port@0 {
132                    reg = <0>;
133                    dpu_intf1_out: endpoint {
134                        remote-endpoint = <&mdss_dsi0_in>;
135                    };
136                };
137            };
138        };
139
140        dsi@5e94000 {
141            compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl";
142            reg = <0x05e94000 0x400>;
143            reg-names = "dsi_ctrl";
144
145            interrupt-parent = <&mdss>;
146            interrupts = <4>;
147
148            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
149                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
150                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
151                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
152                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
153                     <&gcc GCC_DISP_HF_AXI_CLK>;
154            clock-names = "byte",
155                          "byte_intf",
156                          "pixel",
157                          "core",
158                          "iface",
159                          "bus";
160            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
161                      <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
162            assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
163
164            operating-points-v2 = <&dsi_opp_table>;
165            power-domains = <&rpmpd SM6125_VDDCX>;
166
167            phys = <&mdss_dsi0_phy>;
168            phy-names = "dsi";
169
170            #address-cells = <1>;
171            #size-cells = <0>;
172
173            ports {
174                #address-cells = <1>;
175                #size-cells = <0>;
176
177                port@0 {
178                    reg = <0>;
179                    mdss_dsi0_in: endpoint {
180                        remote-endpoint = <&dpu_intf1_out>;
181                    };
182                };
183
184                port@1 {
185                    reg = <1>;
186                    mdss_dsi0_out: endpoint {
187                    };
188                };
189            };
190        };
191
192        phy@5e94400 {
193            compatible = "qcom,sm6125-dsi-phy-14nm";
194            reg = <0x05e94400 0x100>,
195                  <0x05e94500 0x300>,
196                  <0x05e94800 0x188>;
197            reg-names = "dsi_phy",
198                        "dsi_phy_lane",
199                        "dsi_pll";
200
201            #clock-cells = <1>;
202            #phy-cells = <0>;
203
204            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
205                     <&rpmcc RPM_SMD_XO_CLK_SRC>;
206            clock-names = "iface",
207                          "ref";
208
209            required-opps = <&rpmpd_opp_nom>;
210            power-domains = <&rpmpd SM6125_VDDMX>;
211        };
212    };
213...
214