1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SM6115 Display MDSS
8
9maintainers:
10  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
15  are mentioned for SM6115 target.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    items:
22      - const: qcom,sm6115-mdss
23
24  clocks:
25    items:
26      - description: Display AHB clock from gcc
27      - description: Display AXI clock
28      - description: Display core clock
29
30  iommus:
31    maxItems: 2
32
33patternProperties:
34  "^display-controller@[0-9a-f]+$":
35    type: object
36    properties:
37      compatible:
38        const: qcom,sm6115-dpu
39
40  "^dsi@[0-9a-f]+$":
41    type: object
42    properties:
43      compatible:
44        const: qcom,dsi-ctrl-6g-qcm2290
45
46  "^phy@[0-9a-f]+$":
47    type: object
48    properties:
49      compatible:
50        const: qcom,dsi-phy-14nm-2290
51
52required:
53  - compatible
54
55unevaluatedProperties: false
56
57examples:
58  - |
59    #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
60    #include <dt-bindings/clock/qcom,gcc-sm6115.h>
61    #include <dt-bindings/clock/qcom,rpmcc.h>
62    #include <dt-bindings/interrupt-controller/arm-gic.h>
63    #include <dt-bindings/power/qcom-rpmpd.h>
64
65    display-subsystem@5e00000 {
66        #address-cells = <1>;
67        #size-cells = <1>;
68        compatible = "qcom,sm6115-mdss";
69        reg = <0x05e00000 0x1000>;
70        reg-names = "mdss";
71        power-domains = <&dispcc MDSS_GDSC>;
72        clocks = <&gcc GCC_DISP_AHB_CLK>,
73                 <&gcc GCC_DISP_HF_AXI_CLK>,
74                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
75
76        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
77        interrupt-controller;
78        #interrupt-cells = <1>;
79
80        iommus = <&apps_smmu 0x420 0x2>,
81                 <&apps_smmu 0x421 0x0>;
82        ranges;
83
84        display-controller@5e01000 {
85            compatible = "qcom,sm6115-dpu";
86            reg = <0x05e01000 0x8f000>,
87                  <0x05eb0000 0x2008>;
88            reg-names = "mdp", "vbif";
89
90            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
91                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
92                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
93                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
94                     <&dispcc DISP_CC_MDSS_ROT_CLK>,
95                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
96            clock-names = "bus", "iface", "core", "lut", "rot", "vsync";
97
98            operating-points-v2 = <&mdp_opp_table>;
99            power-domains = <&rpmpd SM6115_VDDCX>;
100
101            interrupt-parent = <&mdss>;
102            interrupts = <0>;
103
104            ports {
105                #address-cells = <1>;
106                #size-cells = <0>;
107
108                port@0 {
109                    reg = <0>;
110                    dpu_intf1_out: endpoint {
111                        remote-endpoint = <&dsi0_in>;
112                    };
113                };
114            };
115        };
116
117        dsi@5e94000 {
118            compatible = "qcom,dsi-ctrl-6g-qcm2290";
119            reg = <0x05e94000 0x400>;
120            reg-names = "dsi_ctrl";
121
122            interrupt-parent = <&mdss>;
123            interrupts = <4>;
124
125            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
126                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
127                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
128                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
129                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
130                     <&gcc GCC_DISP_HF_AXI_CLK>;
131            clock-names = "byte",
132                          "byte_intf",
133                          "pixel",
134                          "core",
135                          "iface",
136                          "bus";
137            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
138            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
139
140            operating-points-v2 = <&dsi_opp_table>;
141            power-domains = <&rpmpd SM6115_VDDCX>;
142            phys = <&dsi0_phy>;
143
144            #address-cells = <1>;
145            #size-cells = <0>;
146
147            ports {
148                #address-cells = <1>;
149                #size-cells = <0>;
150
151                port@0 {
152                    reg = <0>;
153                    dsi0_in: endpoint {
154                        remote-endpoint = <&dpu_intf1_out>;
155                    };
156                };
157
158                port@1 {
159                    reg = <1>;
160                    dsi0_out: endpoint {
161                    };
162                };
163            };
164        };
165
166        dsi0_phy: phy@5e94400 {
167            compatible = "qcom,dsi-phy-14nm-2290";
168            reg = <0x05e94400 0x100>,
169                  <0x05e94500 0x300>,
170                  <0x05e94800 0x188>;
171            reg-names = "dsi_phy",
172                        "dsi_phy_lane",
173                        "dsi_pll";
174
175            #clock-cells = <1>;
176            #phy-cells = <0>;
177
178            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
179            clock-names = "iface", "ref";
180        };
181    };
182...
183