1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-dpu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DPU dt properties for SM6115 target 8 9maintainers: 10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> 11 12$ref: /schemas/display/msm/dpu-common.yaml# 13 14properties: 15 compatible: 16 items: 17 - const: qcom,sm6115-dpu 18 19 reg: 20 items: 21 - description: MDP register set 22 - description: VBIF register set 23 24 reg-names: 25 items: 26 - const: mdp 27 - const: vbif 28 29 clocks: 30 items: 31 - description: Display AXI 32 - description: Display AHB 33 - description: Display core 34 - description: Display lut 35 - description: Display rotator 36 - description: Display vsync 37 38 clock-names: 39 items: 40 - const: bus 41 - const: iface 42 - const: core 43 - const: lut 44 - const: rot 45 - const: vsync 46 47required: 48 - compatible 49 - reg 50 - reg-names 51 - clocks 52 - clock-names 53 54unevaluatedProperties: false 55 56examples: 57 - | 58 #include <dt-bindings/clock/qcom,sm6115-dispcc.h> 59 #include <dt-bindings/clock/qcom,gcc-sm6115.h> 60 #include <dt-bindings/power/qcom-rpmpd.h> 61 62 display-controller@5e01000 { 63 compatible = "qcom,sm6115-dpu"; 64 reg = <0x05e01000 0x8f000>, 65 <0x05eb0000 0x2008>; 66 reg-names = "mdp", "vbif"; 67 68 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 69 <&dispcc DISP_CC_MDSS_AHB_CLK>, 70 <&dispcc DISP_CC_MDSS_MDP_CLK>, 71 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 72 <&dispcc DISP_CC_MDSS_ROT_CLK>, 73 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 74 clock-names = "bus", "iface", "core", "lut", "rot", "vsync"; 75 76 operating-points-v2 = <&mdp_opp_table>; 77 power-domains = <&rpmpd SM6115_VDDCX>; 78 79 interrupt-parent = <&mdss>; 80 interrupts = <0>; 81 82 ports { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 port@0 { 87 reg = <0>; 88 endpoint { 89 remote-endpoint = <&dsi0_in>; 90 }; 91 }; 92 }; 93 }; 94... 95