1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDM845 Display MDSS
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15  bindings of MDSS are mentioned for SDM845 target.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    items:
22      - const: qcom,sdm845-mdss
23
24  clocks:
25    items:
26      - description: Display AHB clock from gcc
27      - description: Display core clock
28
29  clock-names:
30    items:
31      - const: iface
32      - const: core
33
34  iommus:
35    maxItems: 2
36
37  interconnects:
38    maxItems: 2
39
40  interconnect-names:
41    maxItems: 2
42
43patternProperties:
44  "^display-controller@[0-9a-f]+$":
45    type: object
46    properties:
47      compatible:
48        const: qcom,sdm845-dpu
49
50  "^dsi@[0-9a-f]+$":
51    type: object
52    properties:
53      compatible:
54        const: qcom,mdss-dsi-ctrl
55
56  "^phy@[0-9a-f]+$":
57    type: object
58    properties:
59      compatible:
60        const: qcom,dsi-phy-10nm
61
62unevaluatedProperties: false
63
64examples:
65  - |
66    #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
67    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
68    #include <dt-bindings/clock/qcom,rpmh.h>
69    #include <dt-bindings/interrupt-controller/arm-gic.h>
70    #include <dt-bindings/power/qcom-rpmpd.h>
71
72    display-subsystem@ae00000 {
73        #address-cells = <1>;
74        #size-cells = <1>;
75        compatible = "qcom,sdm845-mdss";
76        reg = <0x0ae00000 0x1000>;
77        reg-names = "mdss";
78        power-domains = <&dispcc MDSS_GDSC>;
79
80        clocks = <&gcc GCC_DISP_AHB_CLK>,
81                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
82        clock-names = "iface", "core";
83
84        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
85        interrupt-controller;
86        #interrupt-cells = <1>;
87
88        iommus = <&apps_smmu 0x880 0x8>,
89                 <&apps_smmu 0xc80 0x8>;
90        ranges;
91
92        display-controller@ae01000 {
93            compatible = "qcom,sdm845-dpu";
94            reg = <0x0ae01000 0x8f000>,
95                  <0x0aeb0000 0x2008>;
96            reg-names = "mdp", "vbif";
97
98            clocks = <&gcc GCC_DISP_AXI_CLK>,
99                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
100                     <&dispcc DISP_CC_MDSS_AXI_CLK>,
101                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
102                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
103            clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
104
105            interrupt-parent = <&mdss>;
106            interrupts = <0>;
107            power-domains = <&rpmhpd SDM845_CX>;
108            operating-points-v2 = <&mdp_opp_table>;
109
110            ports {
111                #address-cells = <1>;
112                #size-cells = <0>;
113
114                port@0 {
115                    reg = <0>;
116                    dpu_intf1_out: endpoint {
117                        remote-endpoint = <&dsi0_in>;
118                    };
119                };
120
121                port@1 {
122                    reg = <1>;
123                    dpu_intf2_out: endpoint {
124                        remote-endpoint = <&dsi1_in>;
125                    };
126                };
127            };
128        };
129
130        dsi@ae94000 {
131            compatible = "qcom,mdss-dsi-ctrl";
132            reg = <0x0ae94000 0x400>;
133            reg-names = "dsi_ctrl";
134
135            interrupt-parent = <&mdss>;
136            interrupts = <4>;
137
138            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
139                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
140                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
141                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
142                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
143                     <&dispcc DISP_CC_MDSS_AXI_CLK>;
144            clock-names = "byte",
145                          "byte_intf",
146                          "pixel",
147                          "core",
148                          "iface",
149                          "bus";
150            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
151                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
152            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
153
154            operating-points-v2 = <&dsi_opp_table>;
155            power-domains = <&rpmhpd SDM845_CX>;
156
157            phys = <&dsi0_phy>;
158            phy-names = "dsi";
159
160            #address-cells = <1>;
161            #size-cells = <0>;
162
163            ports {
164                #address-cells = <1>;
165                #size-cells = <0>;
166
167                port@0 {
168                    reg = <0>;
169                    dsi0_in: endpoint {
170                        remote-endpoint = <&dpu_intf1_out>;
171                    };
172                };
173
174                port@1 {
175                    reg = <1>;
176                    dsi0_out: endpoint {
177                    };
178                };
179            };
180        };
181
182        dsi0_phy: phy@ae94400 {
183            compatible = "qcom,dsi-phy-10nm";
184            reg = <0x0ae94400 0x200>,
185                  <0x0ae94600 0x280>,
186                  <0x0ae94a00 0x1e0>;
187            reg-names = "dsi_phy",
188                        "dsi_phy_lane",
189                        "dsi_pll";
190
191            #clock-cells = <1>;
192            #phy-cells = <0>;
193
194            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
195                     <&rpmhcc RPMH_CXO_CLK>;
196            clock-names = "iface", "ref";
197            vdds-supply = <&vreg_dsi_phy>;
198        };
199
200        dsi@ae96000 {
201            compatible = "qcom,mdss-dsi-ctrl";
202            reg = <0x0ae96000 0x400>;
203            reg-names = "dsi_ctrl";
204
205            interrupt-parent = <&mdss>;
206            interrupts = <5>;
207
208            clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
209                     <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
210                     <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
211                     <&dispcc DISP_CC_MDSS_ESC1_CLK>,
212                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
213                     <&dispcc DISP_CC_MDSS_AXI_CLK>;
214            clock-names = "byte",
215                          "byte_intf",
216                          "pixel",
217                          "core",
218                          "iface",
219                          "bus";
220            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
221                              <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
222            assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
223
224            operating-points-v2 = <&dsi_opp_table>;
225            power-domains = <&rpmhpd SDM845_CX>;
226
227            phys = <&dsi1_phy>;
228            phy-names = "dsi";
229
230            #address-cells = <1>;
231            #size-cells = <0>;
232
233            ports {
234                #address-cells = <1>;
235                #size-cells = <0>;
236
237                port@0 {
238                    reg = <0>;
239                    dsi1_in: endpoint {
240                        remote-endpoint = <&dpu_intf2_out>;
241                    };
242                };
243
244                port@1 {
245                    reg = <1>;
246                    dsi1_out: endpoint {
247                    };
248                };
249            };
250        };
251
252        dsi1_phy: phy@ae96400 {
253            compatible = "qcom,dsi-phy-10nm";
254            reg = <0x0ae96400 0x200>,
255                  <0x0ae96600 0x280>,
256                  <0x0ae96a00 0x10e>;
257            reg-names = "dsi_phy",
258                        "dsi_phy_lane",
259                        "dsi_pll";
260
261            #clock-cells = <1>;
262            #phy-cells = <0>;
263
264            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
265                     <&rpmhcc RPMH_CXO_CLK>;
266            clock-names = "iface", "ref";
267            vdds-supply = <&vreg_dsi_phy>;
268        };
269    };
270...
271