1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SC7280 Display MDSS
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15  bindings of MDSS are mentioned for SC7280.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,sc7280-mdss
22
23  clocks:
24    items:
25      - description: Display AHB clock from gcc
26      - description: Display AHB clock from dispcc
27      - description: Display core clock
28
29  clock-names:
30    items:
31      - const: iface
32      - const: ahb
33      - const: core
34
35  iommus:
36    maxItems: 1
37
38  interconnects:
39    maxItems: 1
40
41  interconnect-names:
42    maxItems: 1
43
44patternProperties:
45  "^display-controller@[0-9a-f]+$":
46    type: object
47    properties:
48      compatible:
49        const: qcom,sc7280-dpu
50
51  "^displayport-controller@[0-9a-f]+$":
52    type: object
53    properties:
54      compatible:
55        const: qcom,sc7280-dp
56
57  "^dsi@[0-9a-f]+$":
58    type: object
59    properties:
60      compatible:
61        const: qcom,mdss-dsi-ctrl
62
63  "^edp@[0-9a-f]+$":
64    type: object
65    properties:
66      compatible:
67        const: qcom,sc7280-edp
68
69  "^phy@[0-9a-f]+$":
70    type: object
71    properties:
72      compatible:
73        enum:
74          - qcom,sc7280-dsi-phy-7nm
75          - qcom,sc7280-edp-phy
76
77unevaluatedProperties: false
78
79examples:
80  - |
81    #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
82    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
83    #include <dt-bindings/clock/qcom,rpmh.h>
84    #include <dt-bindings/interrupt-controller/arm-gic.h>
85    #include <dt-bindings/interconnect/qcom,sc7280.h>
86    #include <dt-bindings/power/qcom-rpmpd.h>
87
88    display-subsystem@ae00000 {
89        #address-cells = <1>;
90        #size-cells = <1>;
91        compatible = "qcom,sc7280-mdss";
92        reg = <0xae00000 0x1000>;
93        reg-names = "mdss";
94        power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
95        clocks = <&gcc GCC_DISP_AHB_CLK>,
96                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
97                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
98        clock-names = "iface",
99                      "ahb",
100                      "core";
101
102        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
103        interrupt-controller;
104        #interrupt-cells = <1>;
105
106        interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
107        interconnect-names = "mdp0-mem";
108
109        iommus = <&apps_smmu 0x900 0x402>;
110        ranges;
111
112        display-controller@ae01000 {
113            compatible = "qcom,sc7280-dpu";
114            reg = <0x0ae01000 0x8f000>,
115                  <0x0aeb0000 0x2008>;
116
117            reg-names = "mdp", "vbif";
118
119            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
120                     <&gcc GCC_DISP_SF_AXI_CLK>,
121                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
122                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
123                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
124                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
125            clock-names = "bus",
126                          "nrt_bus",
127                          "iface",
128                          "lut",
129                          "core",
130                          "vsync";
131
132            interrupt-parent = <&mdss>;
133            interrupts = <0>;
134            power-domains = <&rpmhpd SC7280_CX>;
135            operating-points-v2 = <&mdp_opp_table>;
136
137            ports {
138                #address-cells = <1>;
139                #size-cells = <0>;
140
141                port@0 {
142                    reg = <0>;
143                    dpu_intf1_out: endpoint {
144                        remote-endpoint = <&dsi0_in>;
145                    };
146                };
147
148                port@1 {
149                    reg = <1>;
150                    dpu_intf5_out: endpoint {
151                        remote-endpoint = <&edp_in>;
152                    };
153                };
154
155                port@2 {
156                    reg = <2>;
157                    dpu_intf0_out: endpoint {
158                        remote-endpoint = <&dp_in>;
159                    };
160                };
161            };
162        };
163
164        dsi@ae94000 {
165            compatible = "qcom,mdss-dsi-ctrl";
166            reg = <0x0ae94000 0x400>;
167            reg-names = "dsi_ctrl";
168
169            interrupt-parent = <&mdss>;
170            interrupts = <4>;
171
172            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
173                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
174                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
175                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
176                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
177                     <&gcc GCC_DISP_HF_AXI_CLK>;
178            clock-names = "byte",
179                          "byte_intf",
180                          "pixel",
181                          "core",
182                          "iface",
183                          "bus";
184
185            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
186                              <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
187            assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
188
189            operating-points-v2 = <&dsi_opp_table>;
190            power-domains = <&rpmhpd SC7280_CX>;
191
192            phys = <&mdss_dsi_phy>;
193            phy-names = "dsi";
194
195            #address-cells = <1>;
196            #size-cells = <0>;
197
198            ports {
199                #address-cells = <1>;
200                #size-cells = <0>;
201
202                port@0 {
203                    reg = <0>;
204                    dsi0_in: endpoint {
205                        remote-endpoint = <&dpu_intf1_out>;
206                    };
207                };
208
209                port@1 {
210                    reg = <1>;
211                    dsi0_out: endpoint {
212                    };
213                };
214            };
215
216            dsi_opp_table: opp-table {
217                compatible = "operating-points-v2";
218
219                opp-187500000 {
220                    opp-hz = /bits/ 64 <187500000>;
221                    required-opps = <&rpmhpd_opp_low_svs>;
222                };
223
224                opp-300000000 {
225                    opp-hz = /bits/ 64 <300000000>;
226                    required-opps = <&rpmhpd_opp_svs>;
227                };
228
229                opp-358000000 {
230                    opp-hz = /bits/ 64 <358000000>;
231                    required-opps = <&rpmhpd_opp_svs_l1>;
232                };
233            };
234        };
235
236        mdss_dsi_phy: phy@ae94400 {
237            compatible = "qcom,sc7280-dsi-phy-7nm";
238            reg = <0x0ae94400 0x200>,
239                  <0x0ae94600 0x280>,
240                  <0x0ae94900 0x280>;
241            reg-names = "dsi_phy",
242                        "dsi_phy_lane",
243                        "dsi_pll";
244
245            #clock-cells = <1>;
246            #phy-cells = <0>;
247
248            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
249                     <&rpmhcc RPMH_CXO_CLK>;
250            clock-names = "iface", "ref";
251
252            vdds-supply = <&vreg_dsi_supply>;
253        };
254
255        edp@aea0000 {
256            compatible = "qcom,sc7280-edp";
257            pinctrl-names = "default";
258            pinctrl-0 = <&edp_hot_plug_det>;
259
260            reg = <0xaea0000 0x200>,
261                  <0xaea0200 0x200>,
262                  <0xaea0400 0xc00>,
263                  <0xaea1000 0x400>;
264
265            interrupt-parent = <&mdss>;
266            interrupts = <14>;
267
268            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
269                     <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
270                     <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
271                     <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
272                     <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
273            clock-names = "core_iface",
274                          "core_aux",
275                          "ctrl_link",
276                          "ctrl_link_iface",
277                          "stream_pixel";
278            assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
279                              <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
280            assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
281
282            phys = <&mdss_edp_phy>;
283            phy-names = "dp";
284
285            operating-points-v2 = <&edp_opp_table>;
286            power-domains = <&rpmhpd SC7280_CX>;
287
288            ports {
289                #address-cells = <1>;
290                #size-cells = <0>;
291
292                port@0 {
293                    reg = <0>;
294                    edp_in: endpoint {
295                        remote-endpoint = <&dpu_intf5_out>;
296                    };
297                };
298
299                port@1 {
300                    reg = <1>;
301                    mdss_edp_out: endpoint { };
302                };
303            };
304
305            edp_opp_table: opp-table {
306                compatible = "operating-points-v2";
307
308                opp-160000000 {
309                    opp-hz = /bits/ 64 <160000000>;
310                    required-opps = <&rpmhpd_opp_low_svs>;
311                };
312
313                opp-270000000 {
314                    opp-hz = /bits/ 64 <270000000>;
315                    required-opps = <&rpmhpd_opp_svs>;
316                };
317
318                opp-540000000 {
319                    opp-hz = /bits/ 64 <540000000>;
320                    required-opps = <&rpmhpd_opp_nom>;
321                };
322
323                opp-810000000 {
324                    opp-hz = /bits/ 64 <810000000>;
325                    required-opps = <&rpmhpd_opp_nom>;
326                };
327            };
328        };
329
330        mdss_edp_phy: phy@aec2a00 {
331            compatible = "qcom,sc7280-edp-phy";
332
333            reg = <0xaec2a00 0x19c>,
334                  <0xaec2200 0xa0>,
335                  <0xaec2600 0xa0>,
336                  <0xaec2000 0x1c0>;
337
338            clocks = <&rpmhcc RPMH_CXO_CLK>,
339                     <&gcc GCC_EDP_CLKREF_EN>;
340            clock-names = "aux",
341                          "cfg_ahb";
342
343            #clock-cells = <1>;
344            #phy-cells = <0>;
345        };
346
347        displayport-controller@ae90000 {
348            compatible = "qcom,sc7280-dp";
349
350            reg = <0xae90000 0x200>,
351                  <0xae90200 0x200>,
352                  <0xae90400 0xc00>,
353                  <0xae91000 0x400>,
354                  <0xae91400 0x400>;
355
356            interrupt-parent = <&mdss>;
357            interrupts = <12>;
358
359            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
360                     <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
361                     <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
362                     <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
363                     <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
364            clock-names = "core_iface",
365                          "core_aux",
366                          "ctrl_link",
367                          "ctrl_link_iface",
368                          "stream_pixel";
369            assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
370                              <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
371            assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
372            phys = <&dp_phy>;
373            phy-names = "dp";
374
375            operating-points-v2 = <&dp_opp_table>;
376            power-domains = <&rpmhpd SC7280_CX>;
377
378            #sound-dai-cells = <0>;
379
380            ports {
381                #address-cells = <1>;
382                #size-cells = <0>;
383
384                port@0 {
385                    reg = <0>;
386                    dp_in: endpoint {
387                        remote-endpoint = <&dpu_intf0_out>;
388                    };
389                };
390
391                port@1 {
392                    reg = <1>;
393                    dp_out: endpoint { };
394                };
395            };
396
397            dp_opp_table: opp-table {
398                compatible = "operating-points-v2";
399
400                opp-160000000 {
401                    opp-hz = /bits/ 64 <160000000>;
402                    required-opps = <&rpmhpd_opp_low_svs>;
403                };
404
405                opp-270000000 {
406                    opp-hz = /bits/ 64 <270000000>;
407                    required-opps = <&rpmhpd_opp_svs>;
408                };
409
410                opp-540000000 {
411                    opp-hz = /bits/ 64 <540000000>;
412                    required-opps = <&rpmhpd_opp_svs_l1>;
413                };
414
415                opp-810000000 {
416                    opp-hz = /bits/ 64 <810000000>;
417                    required-opps = <&rpmhpd_opp_nom>;
418                };
419            };
420        };
421    };
422...
423