1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SC7180 Display MDSS
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12description:
13  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14  sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15  bindings of MDSS are mentioned for SC7180 target.
16
17$ref: /schemas/display/msm/mdss-common.yaml#
18
19properties:
20  compatible:
21    items:
22      - const: qcom,sc7180-mdss
23
24  clocks:
25    items:
26      - description: Display AHB clock from gcc
27      - description: Display AHB clock from dispcc
28      - description: Display core clock
29
30  clock-names:
31    items:
32      - const: iface
33      - const: ahb
34      - const: core
35
36  iommus:
37    maxItems: 1
38
39  interconnects:
40    maxItems: 1
41
42  interconnect-names:
43    maxItems: 1
44
45patternProperties:
46  "^display-controller@[0-9a-f]+$":
47    type: object
48    properties:
49      compatible:
50        const: qcom,sc7180-dpu
51
52  "^displayport-controller@[0-9a-f]+$":
53    type: object
54    properties:
55      compatible:
56        const: qcom,sc7180-dp
57
58  "^dsi@[0-9a-f]+$":
59    type: object
60    properties:
61      compatible:
62        const: qcom,mdss-dsi-ctrl
63
64  "^phy@[0-9a-f]+$":
65    type: object
66    properties:
67      compatible:
68        const: qcom,dsi-phy-10nm
69
70unevaluatedProperties: false
71
72examples:
73  - |
74    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
75    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
76    #include <dt-bindings/clock/qcom,rpmh.h>
77    #include <dt-bindings/interrupt-controller/arm-gic.h>
78    #include <dt-bindings/interconnect/qcom,sdm845.h>
79    #include <dt-bindings/power/qcom-rpmpd.h>
80
81    display-subsystem@ae00000 {
82        #address-cells = <1>;
83        #size-cells = <1>;
84        compatible = "qcom,sc7180-mdss";
85        reg = <0xae00000 0x1000>;
86        reg-names = "mdss";
87        power-domains = <&dispcc MDSS_GDSC>;
88        clocks = <&gcc GCC_DISP_AHB_CLK>,
89                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
90                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
91        clock-names = "iface", "ahb", "core";
92
93        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
94        interrupt-controller;
95        #interrupt-cells = <1>;
96
97        interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
98        interconnect-names = "mdp0-mem";
99
100        iommus = <&apps_smmu 0x800 0x2>;
101        ranges;
102
103        display-controller@ae01000 {
104            compatible = "qcom,sc7180-dpu";
105            reg = <0x0ae01000 0x8f000>,
106                  <0x0aeb0000 0x2008>;
107
108            reg-names = "mdp", "vbif";
109
110            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
111                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
112                     <&dispcc DISP_CC_MDSS_ROT_CLK>,
113                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
114                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
115                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
116            clock-names = "bus", "iface", "rot", "lut", "core",
117                          "vsync";
118
119            interrupt-parent = <&mdss>;
120            interrupts = <0>;
121            power-domains = <&rpmhpd SC7180_CX>;
122            operating-points-v2 = <&mdp_opp_table>;
123
124            ports {
125                #address-cells = <1>;
126                #size-cells = <0>;
127
128                port@0 {
129                    reg = <0>;
130                    dpu_intf1_out: endpoint {
131                        remote-endpoint = <&dsi0_in>;
132                    };
133                };
134
135                port@2 {
136                    reg = <2>;
137                    dpu_intf0_out: endpoint {
138                        remote-endpoint = <&dp_in>;
139                    };
140                };
141            };
142        };
143
144        dsi@ae94000 {
145            compatible = "qcom,mdss-dsi-ctrl";
146            reg = <0x0ae94000 0x400>;
147            reg-names = "dsi_ctrl";
148
149            interrupt-parent = <&mdss>;
150            interrupts = <4>;
151
152            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
153                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
154                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
155                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
156                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
157                     <&gcc GCC_DISP_HF_AXI_CLK>;
158            clock-names = "byte",
159                          "byte_intf",
160                          "pixel",
161                          "core",
162                          "iface",
163                          "bus";
164
165            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
166            assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
167
168            operating-points-v2 = <&dsi_opp_table>;
169            power-domains = <&rpmhpd SC7180_CX>;
170
171            phys = <&dsi_phy>;
172            phy-names = "dsi";
173
174            #address-cells = <1>;
175            #size-cells = <0>;
176
177            ports {
178                #address-cells = <1>;
179                #size-cells = <0>;
180
181                port@0 {
182                    reg = <0>;
183                    dsi0_in: endpoint {
184                        remote-endpoint = <&dpu_intf1_out>;
185                    };
186                };
187
188                port@1 {
189                    reg = <1>;
190                    dsi0_out: endpoint {
191                    };
192                };
193            };
194
195            dsi_opp_table: opp-table {
196                compatible = "operating-points-v2";
197
198                opp-187500000 {
199                    opp-hz = /bits/ 64 <187500000>;
200                    required-opps = <&rpmhpd_opp_low_svs>;
201                };
202
203                opp-300000000 {
204                    opp-hz = /bits/ 64 <300000000>;
205                    required-opps = <&rpmhpd_opp_svs>;
206                };
207
208                opp-358000000 {
209                    opp-hz = /bits/ 64 <358000000>;
210                    required-opps = <&rpmhpd_opp_svs_l1>;
211                };
212            };
213        };
214
215        dsi_phy: phy@ae94400 {
216            compatible = "qcom,dsi-phy-10nm";
217            reg = <0x0ae94400 0x200>,
218                  <0x0ae94600 0x280>,
219                  <0x0ae94a00 0x1e0>;
220            reg-names = "dsi_phy",
221                    "dsi_phy_lane",
222                    "dsi_pll";
223
224            #clock-cells = <1>;
225            #phy-cells = <0>;
226
227            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
228                 <&rpmhcc RPMH_CXO_CLK>;
229            clock-names = "iface", "ref";
230            vdds-supply = <&vreg_dsi_phy>;
231        };
232
233        displayport-controller@ae90000 {
234            compatible = "qcom,sc7180-dp";
235
236            reg = <0xae90000 0x200>,
237                  <0xae90200 0x200>,
238                  <0xae90400 0xc00>,
239                  <0xae91000 0x400>,
240                  <0xae91400 0x400>;
241
242            interrupt-parent = <&mdss>;
243            interrupts = <12>;
244
245            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
246                     <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
247                     <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
248                     <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
249                     <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
250            clock-names = "core_iface", "core_aux", "ctrl_link",
251                          "ctrl_link_iface", "stream_pixel";
252            assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
253                              <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
254            assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
255            phys = <&dp_phy>;
256            phy-names = "dp";
257
258            operating-points-v2 = <&dp_opp_table>;
259            power-domains = <&rpmhpd SC7180_CX>;
260
261            #sound-dai-cells = <0>;
262
263            ports {
264                #address-cells = <1>;
265                #size-cells = <0>;
266                port@0 {
267                    reg = <0>;
268                    dp_in: endpoint {
269                        remote-endpoint = <&dpu_intf0_out>;
270                    };
271                };
272
273                port@1 {
274                    reg = <1>;
275                    dp_out: endpoint { };
276                };
277            };
278
279            dp_opp_table: opp-table {
280                compatible = "operating-points-v2";
281
282                opp-160000000 {
283                    opp-hz = /bits/ 64 <160000000>;
284                    required-opps = <&rpmhpd_opp_low_svs>;
285                };
286
287                opp-270000000 {
288                    opp-hz = /bits/ 64 <270000000>;
289                    required-opps = <&rpmhpd_opp_svs>;
290                };
291
292                opp-540000000 {
293                    opp-hz = /bits/ 64 <540000000>;
294                    required-opps = <&rpmhpd_opp_svs_l1>;
295                };
296
297                opp-810000000 {
298                    opp-hz = /bits/ 64 <810000000>;
299                    required-opps = <&rpmhpd_opp_nom>;
300                };
301            };
302        };
303    };
304...
305