1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/qcom,sc7180-dpu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DPU dt properties for SC7180 target 8 9maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 12$ref: /schemas/display/msm/dpu-common.yaml# 13 14properties: 15 compatible: 16 items: 17 - const: qcom,sc7180-dpu 18 19 reg: 20 items: 21 - description: Address offset and size for mdp register set 22 - description: Address offset and size for vbif register set 23 24 reg-names: 25 items: 26 - const: mdp 27 - const: vbif 28 29 clocks: 30 items: 31 - description: Display hf axi clock 32 - description: Display ahb clock 33 - description: Display rotator clock 34 - description: Display lut clock 35 - description: Display core clock 36 - description: Display vsync clock 37 38 clock-names: 39 items: 40 - const: bus 41 - const: iface 42 - const: rot 43 - const: lut 44 - const: core 45 - const: vsync 46 47unevaluatedProperties: false 48 49examples: 50 - | 51 #include <dt-bindings/clock/qcom,dispcc-sc7180.h> 52 #include <dt-bindings/clock/qcom,gcc-sc7180.h> 53 #include <dt-bindings/power/qcom-rpmpd.h> 54 55 display-controller@ae01000 { 56 compatible = "qcom,sc7180-dpu"; 57 reg = <0x0ae01000 0x8f000>, 58 <0x0aeb0000 0x2008>; 59 60 reg-names = "mdp", "vbif"; 61 62 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 63 <&dispcc DISP_CC_MDSS_AHB_CLK>, 64 <&dispcc DISP_CC_MDSS_ROT_CLK>, 65 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 66 <&dispcc DISP_CC_MDSS_MDP_CLK>, 67 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 68 clock-names = "bus", "iface", "rot", "lut", "core", 69 "vsync"; 70 71 interrupt-parent = <&mdss>; 72 interrupts = <0>; 73 power-domains = <&rpmhpd SC7180_CX>; 74 operating-points-v2 = <&mdp_opp_table>; 75 76 ports { 77 #address-cells = <1>; 78 #size-cells = <0>; 79 80 port@0 { 81 reg = <0>; 82 endpoint { 83 remote-endpoint = <&dsi0_in>; 84 }; 85 }; 86 87 port@2 { 88 reg = <2>; 89 endpoint { 90 remote-endpoint = <&dp_in>; 91 }; 92 }; 93 }; 94 }; 95... 96