1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,sc7180-dpu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DPU on SC7180
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12$ref: /schemas/display/msm/dpu-common.yaml#
13
14properties:
15  compatible:
16    enum:
17      - qcom,sc7180-dpu
18      - qcom,sm6350-dpu
19      - qcom,sm6375-dpu
20
21  reg:
22    items:
23      - description: Address offset and size for mdp register set
24      - description: Address offset and size for vbif register set
25
26  reg-names:
27    items:
28      - const: mdp
29      - const: vbif
30
31  clocks:
32    minItems: 6
33    items:
34      - description: Display hf axi clock
35      - description: Display ahb clock
36      - description: Display rotator clock
37      - description: Display lut clock
38      - description: Display core clock
39      - description: Display vsync clock
40      - description: Display core throttle clock
41
42  clock-names:
43    minItems: 6
44    items:
45      - const: bus
46      - const: iface
47      - const: rot
48      - const: lut
49      - const: core
50      - const: vsync
51      - const: throttle
52
53required:
54  - compatible
55  - reg
56  - reg-names
57  - clocks
58  - clock-names
59
60unevaluatedProperties: false
61
62allOf:
63  - if:
64      properties:
65        compatible:
66          const: qcom,sm6375-dpu
67
68    then:
69      properties:
70        clocks:
71          minItems: 7
72
73        clock-names:
74          minItems: 7
75
76examples:
77  - |
78    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
79    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
80    #include <dt-bindings/power/qcom-rpmpd.h>
81
82    display-controller@ae01000 {
83        compatible = "qcom,sc7180-dpu";
84        reg = <0x0ae01000 0x8f000>,
85              <0x0aeb0000 0x2008>;
86
87        reg-names = "mdp", "vbif";
88
89        clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
90                 <&dispcc DISP_CC_MDSS_AHB_CLK>,
91                 <&dispcc DISP_CC_MDSS_ROT_CLK>,
92                 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
93                 <&dispcc DISP_CC_MDSS_MDP_CLK>,
94                 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
95        clock-names = "bus", "iface", "rot", "lut", "core",
96                      "vsync";
97
98        interrupt-parent = <&mdss>;
99        interrupts = <0>;
100        power-domains = <&rpmhpd SC7180_CX>;
101        operating-points-v2 = <&mdp_opp_table>;
102
103        ports {
104            #address-cells = <1>;
105            #size-cells = <0>;
106
107            port@0 {
108                reg = <0>;
109                endpoint {
110                    remote-endpoint = <&dsi0_in>;
111                };
112            };
113
114            port@2 {
115                reg = <2>;
116                endpoint {
117                    remote-endpoint = <&dp_in>;
118                };
119            };
120        };
121    };
122...
123