xref: /openbmc/linux/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml (revision e65e175b07bef5974045cc42238de99057669ca7) 
1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/qcom,mdss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Mobile Display SubSystem (MDSS)
8
9maintainers:
10  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11  - Rob Clark <robdclark@gmail.com>
12
13description:
14  This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
15  encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
16
17properties:
18  compatible:
19    enum:
20      - qcom,mdss
21
22  reg:
23    minItems: 2
24    maxItems: 3
25
26  reg-names:
27    minItems: 2
28    items:
29      - const: mdss_phys
30      - const: vbif_phys
31      - const: vbif_nrt_phys
32
33  interrupts:
34    maxItems: 1
35
36  interrupt-controller: true
37
38  "#interrupt-cells":
39    const: 1
40
41  power-domains:
42    maxItems: 1
43    description: |
44      The MDSS power domain provided by GCC
45
46  clocks:
47    minItems: 1
48    items:
49      - description: Display abh clock
50      - description: Display axi clock
51      - description: Display vsync clock
52
53  clock-names:
54    minItems: 1
55    items:
56      - const: iface
57      - const: bus
58      - const: vsync
59
60  "#address-cells":
61    const: 1
62
63  "#size-cells":
64    const: 1
65
66  ranges: true
67
68  resets:
69    items:
70      - description: MDSS_CORE reset
71
72required:
73  - compatible
74  - reg
75  - reg-names
76  - interrupts
77  - interrupt-controller
78  - "#interrupt-cells"
79  - power-domains
80  - clocks
81  - clock-names
82  - "#address-cells"
83  - "#size-cells"
84  - ranges
85
86patternProperties:
87  "^mdp@[1-9a-f][0-9a-f]*$":
88    type: object
89    properties:
90      compatible:
91        const: qcom,mdp5
92
93  "^dsi@[1-9a-f][0-9a-f]*$":
94    type: object
95    properties:
96      compatible:
97        const: qcom,mdss-dsi-ctrl
98
99  "^phy@[1-9a-f][0-9a-f]*$":
100    type: object
101    properties:
102      compatible:
103        enum:
104          - qcom,dsi-phy-14nm
105          - qcom,dsi-phy-14nm-660
106          - qcom,dsi-phy-14nm-8953
107          - qcom,dsi-phy-20nm
108          - qcom,dsi-phy-28nm-hpm
109          - qcom,dsi-phy-28nm-lp
110
111  "^hdmi-phy@[1-9a-f][0-9a-f]*$":
112    type: object
113    properties:
114      compatible:
115        enum:
116          - qcom,hdmi-phy-8084
117          - qcom,hdmi-phy-8660
118          - qcom,hdmi-phy-8960
119          - qcom,hdmi-phy-8974
120          - qcom,hdmi-phy-8996
121
122  "^hdmi-tx@[1-9a-f][0-9a-f]*$":
123    type: object
124    properties:
125      compatible:
126        enum:
127          - qcom,hdmi-tx-8084
128          - qcom,hdmi-tx-8660
129          - qcom,hdmi-tx-8960
130          - qcom,hdmi-tx-8974
131          - qcom,hdmi-tx-8994
132          - qcom,hdmi-tx-8996
133
134additionalProperties: false
135
136examples:
137  - |
138    #include <dt-bindings/clock/qcom,gcc-msm8916.h>
139    #include <dt-bindings/interrupt-controller/arm-gic.h>
140    mdss@1a00000 {
141        compatible = "qcom,mdss";
142        reg = <0x1a00000 0x1000>,
143              <0x1ac8000 0x3000>;
144        reg-names = "mdss_phys", "vbif_phys";
145
146        power-domains = <&gcc MDSS_GDSC>;
147
148        clocks = <&gcc GCC_MDSS_AHB_CLK>,
149                 <&gcc GCC_MDSS_AXI_CLK>,
150                 <&gcc GCC_MDSS_VSYNC_CLK>;
151        clock-names = "iface",
152                      "bus",
153                      "vsync";
154
155        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
156
157        interrupt-controller;
158        #interrupt-cells = <1>;
159
160        #address-cells = <1>;
161        #size-cells = <1>;
162        ranges;
163
164        mdp@1a01000 {
165            compatible = "qcom,mdp5";
166            reg = <0x01a01000 0x89000>;
167            reg-names = "mdp_phys";
168
169            interrupt-parent = <&mdss>;
170            interrupts = <0>;
171
172            clocks = <&gcc GCC_MDSS_AHB_CLK>,
173                     <&gcc GCC_MDSS_AXI_CLK>,
174                     <&gcc GCC_MDSS_MDP_CLK>,
175                     <&gcc GCC_MDSS_VSYNC_CLK>;
176            clock-names = "iface",
177                      "bus",
178                      "core",
179                      "vsync";
180
181            iommus = <&apps_iommu 4>;
182
183            ports {
184                #address-cells = <1>;
185                #size-cells = <0>;
186
187                port@0 {
188                    reg = <0>;
189                    mdp5_intf1_out: endpoint {
190                        remote-endpoint = <&dsi0_in>;
191                    };
192                };
193            };
194        };
195    };
196...
197