1*2a5c1021SKonrad Dybcio# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2*2a5c1021SKonrad Dybcio%YAML 1.2 3*2a5c1021SKonrad Dybcio--- 4*2a5c1021SKonrad Dybcio$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml# 5*2a5c1021SKonrad Dybcio$schema: http://devicetree.org/meta-schemas/core.yaml# 6*2a5c1021SKonrad Dybcio 7*2a5c1021SKonrad Dybciotitle: Qualcomm SM6375 Display MDSS 8*2a5c1021SKonrad Dybcio 9*2a5c1021SKonrad Dybciomaintainers: 10*2a5c1021SKonrad Dybcio - Konrad Dybcio <konrad.dybcio@linaro.org> 11*2a5c1021SKonrad Dybcio 12*2a5c1021SKonrad Dybciodescription: 13*2a5c1021SKonrad Dybcio SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks 14*2a5c1021SKonrad Dybcio like DPU display controller, DSI and DP interfaces etc. 15*2a5c1021SKonrad Dybcio 16*2a5c1021SKonrad Dybcio$ref: /schemas/display/msm/mdss-common.yaml# 17*2a5c1021SKonrad Dybcio 18*2a5c1021SKonrad Dybcioproperties: 19*2a5c1021SKonrad Dybcio compatible: 20*2a5c1021SKonrad Dybcio const: qcom,sm6375-mdss 21*2a5c1021SKonrad Dybcio 22*2a5c1021SKonrad Dybcio clocks: 23*2a5c1021SKonrad Dybcio items: 24*2a5c1021SKonrad Dybcio - description: Display AHB clock from gcc 25*2a5c1021SKonrad Dybcio - description: Display AHB clock 26*2a5c1021SKonrad Dybcio - description: Display core clock 27*2a5c1021SKonrad Dybcio 28*2a5c1021SKonrad Dybcio clock-names: 29*2a5c1021SKonrad Dybcio items: 30*2a5c1021SKonrad Dybcio - const: iface 31*2a5c1021SKonrad Dybcio - const: ahb 32*2a5c1021SKonrad Dybcio - const: core 33*2a5c1021SKonrad Dybcio 34*2a5c1021SKonrad Dybcio iommus: 35*2a5c1021SKonrad Dybcio maxItems: 1 36*2a5c1021SKonrad Dybcio 37*2a5c1021SKonrad Dybcio interconnects: 38*2a5c1021SKonrad Dybcio maxItems: 2 39*2a5c1021SKonrad Dybcio 40*2a5c1021SKonrad Dybcio interconnect-names: 41*2a5c1021SKonrad Dybcio maxItems: 2 42*2a5c1021SKonrad Dybcio 43*2a5c1021SKonrad DybciopatternProperties: 44*2a5c1021SKonrad Dybcio "^display-controller@[0-9a-f]+$": 45*2a5c1021SKonrad Dybcio type: object 46*2a5c1021SKonrad Dybcio properties: 47*2a5c1021SKonrad Dybcio compatible: 48*2a5c1021SKonrad Dybcio const: qcom,sm6375-dpu 49*2a5c1021SKonrad Dybcio 50*2a5c1021SKonrad Dybcio "^dsi@[0-9a-f]+$": 51*2a5c1021SKonrad Dybcio type: object 52*2a5c1021SKonrad Dybcio properties: 53*2a5c1021SKonrad Dybcio compatible: 54*2a5c1021SKonrad Dybcio items: 55*2a5c1021SKonrad Dybcio - const: qcom,sm6375-dsi-ctrl 56*2a5c1021SKonrad Dybcio - const: qcom,mdss-dsi-ctrl 57*2a5c1021SKonrad Dybcio 58*2a5c1021SKonrad Dybcio "^phy@[0-9a-f]+$": 59*2a5c1021SKonrad Dybcio type: object 60*2a5c1021SKonrad Dybcio properties: 61*2a5c1021SKonrad Dybcio compatible: 62*2a5c1021SKonrad Dybcio const: qcom,sm6375-dsi-phy-7nm 63*2a5c1021SKonrad Dybcio 64*2a5c1021SKonrad DybciounevaluatedProperties: false 65*2a5c1021SKonrad Dybcio 66*2a5c1021SKonrad Dybcioexamples: 67*2a5c1021SKonrad Dybcio - | 68*2a5c1021SKonrad Dybcio #include <dt-bindings/clock/qcom,rpmcc.h> 69*2a5c1021SKonrad Dybcio #include <dt-bindings/clock/qcom,sm6375-gcc.h> 70*2a5c1021SKonrad Dybcio #include <dt-bindings/clock/qcom,sm6375-dispcc.h> 71*2a5c1021SKonrad Dybcio #include <dt-bindings/interrupt-controller/arm-gic.h> 72*2a5c1021SKonrad Dybcio #include <dt-bindings/power/qcom-rpmpd.h> 73*2a5c1021SKonrad Dybcio 74*2a5c1021SKonrad Dybcio display-subsystem@5e00000 { 75*2a5c1021SKonrad Dybcio compatible = "qcom,sm6375-mdss"; 76*2a5c1021SKonrad Dybcio reg = <0x05e00000 0x1000>; 77*2a5c1021SKonrad Dybcio reg-names = "mdss"; 78*2a5c1021SKonrad Dybcio 79*2a5c1021SKonrad Dybcio power-domains = <&dispcc MDSS_GDSC>; 80*2a5c1021SKonrad Dybcio 81*2a5c1021SKonrad Dybcio clocks = <&gcc GCC_DISP_AHB_CLK>, 82*2a5c1021SKonrad Dybcio <&dispcc DISP_CC_MDSS_AHB_CLK>, 83*2a5c1021SKonrad Dybcio <&dispcc DISP_CC_MDSS_MDP_CLK>; 84*2a5c1021SKonrad Dybcio clock-names = "iface", "ahb", "core"; 85*2a5c1021SKonrad Dybcio 86*2a5c1021SKonrad Dybcio interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 87*2a5c1021SKonrad Dybcio interrupt-controller; 88*2a5c1021SKonrad Dybcio #interrupt-cells = <1>; 89*2a5c1021SKonrad Dybcio 90*2a5c1021SKonrad Dybcio iommus = <&apps_smmu 0x820 0x2>; 91*2a5c1021SKonrad Dybcio #address-cells = <1>; 92*2a5c1021SKonrad Dybcio #size-cells = <1>; 93*2a5c1021SKonrad Dybcio ranges; 94*2a5c1021SKonrad Dybcio 95*2a5c1021SKonrad Dybcio display-controller@5e01000 { 96*2a5c1021SKonrad Dybcio compatible = "qcom,sm6375-dpu"; 97*2a5c1021SKonrad Dybcio reg = <0x05e01000 0x8e030>, 98*2a5c1021SKonrad Dybcio <0x05eb0000 0x2008>; 99*2a5c1021SKonrad Dybcio reg-names = "mdp", "vbif"; 100*2a5c1021SKonrad Dybcio 101*2a5c1021SKonrad Dybcio clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 102*2a5c1021SKonrad Dybcio <&dispcc DISP_CC_MDSS_AHB_CLK>, 103*2a5c1021SKonrad Dybcio <&dispcc DISP_CC_MDSS_ROT_CLK>, 104*2a5c1021SKonrad Dybcio <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 105*2a5c1021SKonrad Dybcio <&dispcc DISP_CC_MDSS_MDP_CLK>, 106*2a5c1021SKonrad Dybcio <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 107*2a5c1021SKonrad Dybcio <&gcc GCC_DISP_THROTTLE_CORE_CLK>; 108*2a5c1021SKonrad Dybcio clock-names = "bus", 109*2a5c1021SKonrad Dybcio "iface", 110*2a5c1021SKonrad Dybcio "rot", 111*2a5c1021SKonrad Dybcio "lut", 112*2a5c1021SKonrad Dybcio "core", 113*2a5c1021SKonrad Dybcio "vsync", 114*2a5c1021SKonrad Dybcio "throttle"; 115*2a5c1021SKonrad Dybcio 116*2a5c1021SKonrad Dybcio assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 117*2a5c1021SKonrad Dybcio assigned-clock-rates = <19200000>; 118*2a5c1021SKonrad Dybcio 119*2a5c1021SKonrad Dybcio operating-points-v2 = <&mdp_opp_table>; 120*2a5c1021SKonrad Dybcio power-domains = <&rpmpd SM6375_VDDCX>; 121*2a5c1021SKonrad Dybcio 122*2a5c1021SKonrad Dybcio interrupt-parent = <&mdss>; 123*2a5c1021SKonrad Dybcio interrupts = <0>; 124*2a5c1021SKonrad Dybcio 125*2a5c1021SKonrad Dybcio ports { 126*2a5c1021SKonrad Dybcio #address-cells = <1>; 127*2a5c1021SKonrad Dybcio #size-cells = <0>; 128*2a5c1021SKonrad Dybcio 129*2a5c1021SKonrad Dybcio port@0 { 130*2a5c1021SKonrad Dybcio reg = <0>; 131*2a5c1021SKonrad Dybcio dpu_intf1_out: endpoint { 132*2a5c1021SKonrad Dybcio remote-endpoint = <&dsi0_in>; 133*2a5c1021SKonrad Dybcio }; 134*2a5c1021SKonrad Dybcio }; 135*2a5c1021SKonrad Dybcio 136*2a5c1021SKonrad Dybcio port@1 { 137*2a5c1021SKonrad Dybcio reg = <1>; 138*2a5c1021SKonrad Dybcio dpu_intf2_out: endpoint { 139*2a5c1021SKonrad Dybcio remote-endpoint = <&dsi1_in>; 140*2a5c1021SKonrad Dybcio }; 141*2a5c1021SKonrad Dybcio }; 142*2a5c1021SKonrad Dybcio }; 143*2a5c1021SKonrad Dybcio }; 144*2a5c1021SKonrad Dybcio 145*2a5c1021SKonrad Dybcio dsi@5e94000 { 146*2a5c1021SKonrad Dybcio compatible = "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 147*2a5c1021SKonrad Dybcio reg = <0x05e94000 0x400>; 148*2a5c1021SKonrad Dybcio reg-names = "dsi_ctrl"; 149*2a5c1021SKonrad Dybcio 150*2a5c1021SKonrad Dybcio interrupt-parent = <&mdss>; 151*2a5c1021SKonrad Dybcio interrupts = <4>; 152*2a5c1021SKonrad Dybcio 153*2a5c1021SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 154*2a5c1021SKonrad Dybcio <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 155*2a5c1021SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 156*2a5c1021SKonrad Dybcio <&dispcc DISP_CC_MDSS_ESC0_CLK>, 157*2a5c1021SKonrad Dybcio <&dispcc DISP_CC_MDSS_AHB_CLK>, 158*2a5c1021SKonrad Dybcio <&gcc GCC_DISP_HF_AXI_CLK>; 159*2a5c1021SKonrad Dybcio clock-names = "byte", 160*2a5c1021SKonrad Dybcio "byte_intf", 161*2a5c1021SKonrad Dybcio "pixel", 162*2a5c1021SKonrad Dybcio "core", 163*2a5c1021SKonrad Dybcio "iface", 164*2a5c1021SKonrad Dybcio "bus"; 165*2a5c1021SKonrad Dybcio 166*2a5c1021SKonrad Dybcio assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 167*2a5c1021SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 168*2a5c1021SKonrad Dybcio assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 169*2a5c1021SKonrad Dybcio 170*2a5c1021SKonrad Dybcio operating-points-v2 = <&dsi_opp_table>; 171*2a5c1021SKonrad Dybcio power-domains = <&rpmpd SM6375_VDDMX>; 172*2a5c1021SKonrad Dybcio 173*2a5c1021SKonrad Dybcio phys = <&mdss_dsi0_phy>; 174*2a5c1021SKonrad Dybcio phy-names = "dsi"; 175*2a5c1021SKonrad Dybcio 176*2a5c1021SKonrad Dybcio #address-cells = <1>; 177*2a5c1021SKonrad Dybcio #size-cells = <0>; 178*2a5c1021SKonrad Dybcio 179*2a5c1021SKonrad Dybcio ports { 180*2a5c1021SKonrad Dybcio #address-cells = <1>; 181*2a5c1021SKonrad Dybcio #size-cells = <0>; 182*2a5c1021SKonrad Dybcio 183*2a5c1021SKonrad Dybcio port@0 { 184*2a5c1021SKonrad Dybcio reg = <0>; 185*2a5c1021SKonrad Dybcio dsi0_in: endpoint { 186*2a5c1021SKonrad Dybcio remote-endpoint = <&dpu_intf1_out>; 187*2a5c1021SKonrad Dybcio }; 188*2a5c1021SKonrad Dybcio }; 189*2a5c1021SKonrad Dybcio 190*2a5c1021SKonrad Dybcio port@1 { 191*2a5c1021SKonrad Dybcio reg = <1>; 192*2a5c1021SKonrad Dybcio dsi0_out: endpoint { 193*2a5c1021SKonrad Dybcio }; 194*2a5c1021SKonrad Dybcio }; 195*2a5c1021SKonrad Dybcio }; 196*2a5c1021SKonrad Dybcio }; 197*2a5c1021SKonrad Dybcio 198*2a5c1021SKonrad Dybcio mdss_dsi0_phy: phy@5e94400 { 199*2a5c1021SKonrad Dybcio compatible = "qcom,sm6375-dsi-phy-7nm"; 200*2a5c1021SKonrad Dybcio reg = <0x05e94400 0x200>, 201*2a5c1021SKonrad Dybcio <0x05e94600 0x280>, 202*2a5c1021SKonrad Dybcio <0x05e94900 0x264>; 203*2a5c1021SKonrad Dybcio reg-names = "dsi_phy", 204*2a5c1021SKonrad Dybcio "dsi_phy_lane", 205*2a5c1021SKonrad Dybcio "dsi_pll"; 206*2a5c1021SKonrad Dybcio 207*2a5c1021SKonrad Dybcio #clock-cells = <1>; 208*2a5c1021SKonrad Dybcio #phy-cells = <0>; 209*2a5c1021SKonrad Dybcio 210*2a5c1021SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 211*2a5c1021SKonrad Dybcio <&rpmcc RPM_SMD_XO_CLK_SRC>; 212*2a5c1021SKonrad Dybcio clock-names = "iface", "ref"; 213*2a5c1021SKonrad Dybcio }; 214*2a5c1021SKonrad Dybcio }; 215*2a5c1021SKonrad Dybcio... 216