1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/qcom,sc8280xp-mdss.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SC8280XP Mobile Display Subsystem 8 9maintainers: 10 - Bjorn Andersson <andersson@kernel.org> 11 12description: 13 Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates 14 sub-blocks like DPU display controller, DSI and DP interfaces etc. 15 16$ref: /schemas/display/msm/mdss-common.yaml# 17 18properties: 19 compatible: 20 const: qcom,sc8280xp-mdss 21 22 clocks: 23 items: 24 - description: Display AHB clock from gcc 25 - description: Display AHB clock from dispcc 26 - description: Display core clock 27 28 clock-names: 29 items: 30 - const: iface 31 - const: ahb 32 - const: core 33 34patternProperties: 35 "^display-controller@[0-9a-f]+$": 36 type: object 37 properties: 38 compatible: 39 const: qcom,sc8280xp-dpu 40 41unevaluatedProperties: false 42 43examples: 44 - | 45 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 46 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 47 #include <dt-bindings/interrupt-controller/arm-gic.h> 48 #include <dt-bindings/interconnect/qcom,sc8280xp.h> 49 #include <dt-bindings/power/qcom-rpmpd.h> 50 51 display-subsystem@ae00000 { 52 compatible = "qcom,sc8280xp-mdss"; 53 reg = <0x0ae00000 0x1000>; 54 reg-names = "mdss"; 55 56 power-domains = <&dispcc0 MDSS_GDSC>; 57 58 clocks = <&gcc GCC_DISP_AHB_CLK>, 59 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 60 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 61 clock-names = "iface", 62 "ahb", 63 "core"; 64 65 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 66 67 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 68 interrupt-controller; 69 #interrupt-cells = <1>; 70 71 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 72 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 73 interconnect-names = "mdp0-mem", "mdp1-mem"; 74 75 iommus = <&apps_smmu 0x1000 0x402>; 76 77 #address-cells = <1>; 78 #size-cells = <1>; 79 ranges; 80 81 display-controller@ae01000 { 82 compatible = "qcom,sc8280xp-dpu"; 83 reg = <0x0ae01000 0x8f000>, 84 <0x0aeb0000 0x2008>; 85 reg-names = "mdp", "vbif"; 86 87 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 88 <&gcc GCC_DISP_SF_AXI_CLK>, 89 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 90 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 91 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 92 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 93 clock-names = "bus", 94 "nrt_bus", 95 "iface", 96 "lut", 97 "core", 98 "vsync"; 99 100 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 101 assigned-clock-rates = <19200000>; 102 103 operating-points-v2 = <&mdss0_mdp_opp_table>; 104 power-domains = <&rpmhpd SC8280XP_MMCX>; 105 106 interrupt-parent = <&mdss0>; 107 interrupts = <0>; 108 109 ports { 110 #address-cells = <1>; 111 #size-cells = <0>; 112 113 port@0 { 114 reg = <0>; 115 endpoint { 116 remote-endpoint = <&mdss0_dp0_in>; 117 }; 118 }; 119 120 port@4 { 121 reg = <4>; 122 endpoint { 123 remote-endpoint = <&mdss0_dp1_in>; 124 }; 125 }; 126 127 port@5 { 128 reg = <5>; 129 endpoint { 130 remote-endpoint = <&mdss0_dp3_in>; 131 }; 132 }; 133 134 port@6 { 135 reg = <6>; 136 endpoint { 137 remote-endpoint = <&mdss0_dp2_in>; 138 }; 139 }; 140 }; 141 }; 142 }; 143... 144