1aba04b0dSDmitry Baryshkov# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2aba04b0dSDmitry Baryshkov%YAML 1.2 3aba04b0dSDmitry Baryshkov--- 4aba04b0dSDmitry Baryshkov$id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mdss.yaml# 5aba04b0dSDmitry Baryshkov$schema: http://devicetree.org/meta-schemas/core.yaml# 6aba04b0dSDmitry Baryshkov 7aba04b0dSDmitry Baryshkovtitle: Qualcomm SC7180 Display MDSS 8aba04b0dSDmitry Baryshkov 9aba04b0dSDmitry Baryshkovmaintainers: 10aba04b0dSDmitry Baryshkov - Krishna Manikandan <quic_mkrishn@quicinc.com> 11aba04b0dSDmitry Baryshkov 12aba04b0dSDmitry Baryshkovdescription: 13aba04b0dSDmitry Baryshkov Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates 14aba04b0dSDmitry Baryshkov sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree 15aba04b0dSDmitry Baryshkov bindings of MDSS are mentioned for SC7180 target. 16aba04b0dSDmitry Baryshkov 17aba04b0dSDmitry Baryshkov$ref: /schemas/display/msm/mdss-common.yaml# 18aba04b0dSDmitry Baryshkov 19aba04b0dSDmitry Baryshkovproperties: 20aba04b0dSDmitry Baryshkov compatible: 21aba04b0dSDmitry Baryshkov items: 22aba04b0dSDmitry Baryshkov - const: qcom,sc7180-mdss 23aba04b0dSDmitry Baryshkov 24aba04b0dSDmitry Baryshkov clocks: 25aba04b0dSDmitry Baryshkov items: 26aba04b0dSDmitry Baryshkov - description: Display AHB clock from gcc 27aba04b0dSDmitry Baryshkov - description: Display AHB clock from dispcc 28aba04b0dSDmitry Baryshkov - description: Display core clock 29aba04b0dSDmitry Baryshkov 30aba04b0dSDmitry Baryshkov clock-names: 31aba04b0dSDmitry Baryshkov items: 32aba04b0dSDmitry Baryshkov - const: iface 33aba04b0dSDmitry Baryshkov - const: ahb 34aba04b0dSDmitry Baryshkov - const: core 35aba04b0dSDmitry Baryshkov 36aba04b0dSDmitry Baryshkov iommus: 37aba04b0dSDmitry Baryshkov maxItems: 1 38aba04b0dSDmitry Baryshkov 39aba04b0dSDmitry Baryshkov interconnects: 40aba04b0dSDmitry Baryshkov maxItems: 1 41aba04b0dSDmitry Baryshkov 42aba04b0dSDmitry Baryshkov interconnect-names: 43aba04b0dSDmitry Baryshkov maxItems: 1 44aba04b0dSDmitry Baryshkov 45aba04b0dSDmitry BaryshkovpatternProperties: 46aba04b0dSDmitry Baryshkov "^display-controller@[0-9a-f]+$": 47aba04b0dSDmitry Baryshkov type: object 48aba04b0dSDmitry Baryshkov properties: 49aba04b0dSDmitry Baryshkov compatible: 50aba04b0dSDmitry Baryshkov const: qcom,sc7180-dpu 51aba04b0dSDmitry Baryshkov 524b32e466SDmitry Baryshkov "^displayport-controller@[0-9a-f]+$": 534b32e466SDmitry Baryshkov type: object 544b32e466SDmitry Baryshkov properties: 554b32e466SDmitry Baryshkov compatible: 564b32e466SDmitry Baryshkov const: qcom,sc7180-dp 574b32e466SDmitry Baryshkov 584b32e466SDmitry Baryshkov "^dsi@[0-9a-f]+$": 594b32e466SDmitry Baryshkov type: object 604b32e466SDmitry Baryshkov properties: 614b32e466SDmitry Baryshkov compatible: 624b32e466SDmitry Baryshkov const: qcom,mdss-dsi-ctrl 634b32e466SDmitry Baryshkov 644b32e466SDmitry Baryshkov "^phy@[0-9a-f]+$": 654b32e466SDmitry Baryshkov type: object 664b32e466SDmitry Baryshkov properties: 674b32e466SDmitry Baryshkov compatible: 684b32e466SDmitry Baryshkov const: qcom,dsi-phy-10nm 694b32e466SDmitry Baryshkov 70*e96150a6SDmitry Baryshkovrequired: 71*e96150a6SDmitry Baryshkov - compatible 72*e96150a6SDmitry Baryshkov 73aba04b0dSDmitry BaryshkovunevaluatedProperties: false 74aba04b0dSDmitry Baryshkov 75aba04b0dSDmitry Baryshkovexamples: 76aba04b0dSDmitry Baryshkov - | 77aba04b0dSDmitry Baryshkov #include <dt-bindings/clock/qcom,dispcc-sc7180.h> 78aba04b0dSDmitry Baryshkov #include <dt-bindings/clock/qcom,gcc-sc7180.h> 794b32e466SDmitry Baryshkov #include <dt-bindings/clock/qcom,rpmh.h> 80aba04b0dSDmitry Baryshkov #include <dt-bindings/interrupt-controller/arm-gic.h> 81aba04b0dSDmitry Baryshkov #include <dt-bindings/interconnect/qcom,sdm845.h> 82aba04b0dSDmitry Baryshkov #include <dt-bindings/power/qcom-rpmpd.h> 83aba04b0dSDmitry Baryshkov 84aba04b0dSDmitry Baryshkov display-subsystem@ae00000 { 85aba04b0dSDmitry Baryshkov #address-cells = <1>; 86aba04b0dSDmitry Baryshkov #size-cells = <1>; 87aba04b0dSDmitry Baryshkov compatible = "qcom,sc7180-mdss"; 88aba04b0dSDmitry Baryshkov reg = <0xae00000 0x1000>; 89aba04b0dSDmitry Baryshkov reg-names = "mdss"; 90aba04b0dSDmitry Baryshkov power-domains = <&dispcc MDSS_GDSC>; 91aba04b0dSDmitry Baryshkov clocks = <&gcc GCC_DISP_AHB_CLK>, 92aba04b0dSDmitry Baryshkov <&dispcc DISP_CC_MDSS_AHB_CLK>, 93aba04b0dSDmitry Baryshkov <&dispcc DISP_CC_MDSS_MDP_CLK>; 94aba04b0dSDmitry Baryshkov clock-names = "iface", "ahb", "core"; 95aba04b0dSDmitry Baryshkov 96aba04b0dSDmitry Baryshkov interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 97aba04b0dSDmitry Baryshkov interrupt-controller; 98aba04b0dSDmitry Baryshkov #interrupt-cells = <1>; 99aba04b0dSDmitry Baryshkov 100aba04b0dSDmitry Baryshkov interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; 101aba04b0dSDmitry Baryshkov interconnect-names = "mdp0-mem"; 102aba04b0dSDmitry Baryshkov 103aba04b0dSDmitry Baryshkov iommus = <&apps_smmu 0x800 0x2>; 104aba04b0dSDmitry Baryshkov ranges; 105aba04b0dSDmitry Baryshkov 106aba04b0dSDmitry Baryshkov display-controller@ae01000 { 107aba04b0dSDmitry Baryshkov compatible = "qcom,sc7180-dpu"; 108aba04b0dSDmitry Baryshkov reg = <0x0ae01000 0x8f000>, 109aba04b0dSDmitry Baryshkov <0x0aeb0000 0x2008>; 110aba04b0dSDmitry Baryshkov 111aba04b0dSDmitry Baryshkov reg-names = "mdp", "vbif"; 112aba04b0dSDmitry Baryshkov 113aba04b0dSDmitry Baryshkov clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 114aba04b0dSDmitry Baryshkov <&dispcc DISP_CC_MDSS_AHB_CLK>, 115aba04b0dSDmitry Baryshkov <&dispcc DISP_CC_MDSS_ROT_CLK>, 116aba04b0dSDmitry Baryshkov <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 117aba04b0dSDmitry Baryshkov <&dispcc DISP_CC_MDSS_MDP_CLK>, 118aba04b0dSDmitry Baryshkov <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 119aba04b0dSDmitry Baryshkov clock-names = "bus", "iface", "rot", "lut", "core", 120aba04b0dSDmitry Baryshkov "vsync"; 121aba04b0dSDmitry Baryshkov 122aba04b0dSDmitry Baryshkov interrupt-parent = <&mdss>; 123aba04b0dSDmitry Baryshkov interrupts = <0>; 124aba04b0dSDmitry Baryshkov power-domains = <&rpmhpd SC7180_CX>; 125aba04b0dSDmitry Baryshkov operating-points-v2 = <&mdp_opp_table>; 126aba04b0dSDmitry Baryshkov 127aba04b0dSDmitry Baryshkov ports { 128aba04b0dSDmitry Baryshkov #address-cells = <1>; 129aba04b0dSDmitry Baryshkov #size-cells = <0>; 130aba04b0dSDmitry Baryshkov 131aba04b0dSDmitry Baryshkov port@0 { 132aba04b0dSDmitry Baryshkov reg = <0>; 133aba04b0dSDmitry Baryshkov dpu_intf1_out: endpoint { 134aba04b0dSDmitry Baryshkov remote-endpoint = <&dsi0_in>; 135aba04b0dSDmitry Baryshkov }; 136aba04b0dSDmitry Baryshkov }; 137aba04b0dSDmitry Baryshkov 138aba04b0dSDmitry Baryshkov port@2 { 139aba04b0dSDmitry Baryshkov reg = <2>; 140aba04b0dSDmitry Baryshkov dpu_intf0_out: endpoint { 141aba04b0dSDmitry Baryshkov remote-endpoint = <&dp_in>; 142aba04b0dSDmitry Baryshkov }; 143aba04b0dSDmitry Baryshkov }; 144aba04b0dSDmitry Baryshkov }; 145aba04b0dSDmitry Baryshkov }; 1464b32e466SDmitry Baryshkov 1474b32e466SDmitry Baryshkov dsi@ae94000 { 1484b32e466SDmitry Baryshkov compatible = "qcom,mdss-dsi-ctrl"; 1494b32e466SDmitry Baryshkov reg = <0x0ae94000 0x400>; 1504b32e466SDmitry Baryshkov reg-names = "dsi_ctrl"; 1514b32e466SDmitry Baryshkov 1524b32e466SDmitry Baryshkov interrupt-parent = <&mdss>; 1534b32e466SDmitry Baryshkov interrupts = <4>; 1544b32e466SDmitry Baryshkov 1554b32e466SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1564b32e466SDmitry Baryshkov <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1574b32e466SDmitry Baryshkov <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1584b32e466SDmitry Baryshkov <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1594b32e466SDmitry Baryshkov <&dispcc DISP_CC_MDSS_AHB_CLK>, 1604b32e466SDmitry Baryshkov <&gcc GCC_DISP_HF_AXI_CLK>; 1614b32e466SDmitry Baryshkov clock-names = "byte", 1624b32e466SDmitry Baryshkov "byte_intf", 1634b32e466SDmitry Baryshkov "pixel", 1644b32e466SDmitry Baryshkov "core", 1654b32e466SDmitry Baryshkov "iface", 1664b32e466SDmitry Baryshkov "bus"; 1674b32e466SDmitry Baryshkov 1684b32e466SDmitry Baryshkov assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1694b32e466SDmitry Baryshkov assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 1704b32e466SDmitry Baryshkov 1714b32e466SDmitry Baryshkov operating-points-v2 = <&dsi_opp_table>; 1724b32e466SDmitry Baryshkov power-domains = <&rpmhpd SC7180_CX>; 1734b32e466SDmitry Baryshkov 1744b32e466SDmitry Baryshkov phys = <&dsi_phy>; 1754b32e466SDmitry Baryshkov phy-names = "dsi"; 1764b32e466SDmitry Baryshkov 1774b32e466SDmitry Baryshkov #address-cells = <1>; 1784b32e466SDmitry Baryshkov #size-cells = <0>; 1794b32e466SDmitry Baryshkov 1804b32e466SDmitry Baryshkov ports { 1814b32e466SDmitry Baryshkov #address-cells = <1>; 1824b32e466SDmitry Baryshkov #size-cells = <0>; 1834b32e466SDmitry Baryshkov 1844b32e466SDmitry Baryshkov port@0 { 1854b32e466SDmitry Baryshkov reg = <0>; 1864b32e466SDmitry Baryshkov dsi0_in: endpoint { 1874b32e466SDmitry Baryshkov remote-endpoint = <&dpu_intf1_out>; 1884b32e466SDmitry Baryshkov }; 1894b32e466SDmitry Baryshkov }; 1904b32e466SDmitry Baryshkov 1914b32e466SDmitry Baryshkov port@1 { 1924b32e466SDmitry Baryshkov reg = <1>; 1934b32e466SDmitry Baryshkov dsi0_out: endpoint { 1944b32e466SDmitry Baryshkov }; 1954b32e466SDmitry Baryshkov }; 1964b32e466SDmitry Baryshkov }; 1974b32e466SDmitry Baryshkov 1984b32e466SDmitry Baryshkov dsi_opp_table: opp-table { 1994b32e466SDmitry Baryshkov compatible = "operating-points-v2"; 2004b32e466SDmitry Baryshkov 2014b32e466SDmitry Baryshkov opp-187500000 { 2024b32e466SDmitry Baryshkov opp-hz = /bits/ 64 <187500000>; 2034b32e466SDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 2044b32e466SDmitry Baryshkov }; 2054b32e466SDmitry Baryshkov 2064b32e466SDmitry Baryshkov opp-300000000 { 2074b32e466SDmitry Baryshkov opp-hz = /bits/ 64 <300000000>; 2084b32e466SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs>; 2094b32e466SDmitry Baryshkov }; 2104b32e466SDmitry Baryshkov 2114b32e466SDmitry Baryshkov opp-358000000 { 2124b32e466SDmitry Baryshkov opp-hz = /bits/ 64 <358000000>; 2134b32e466SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs_l1>; 2144b32e466SDmitry Baryshkov }; 2154b32e466SDmitry Baryshkov }; 2164b32e466SDmitry Baryshkov }; 2174b32e466SDmitry Baryshkov 2184b32e466SDmitry Baryshkov dsi_phy: phy@ae94400 { 2194b32e466SDmitry Baryshkov compatible = "qcom,dsi-phy-10nm"; 2204b32e466SDmitry Baryshkov reg = <0x0ae94400 0x200>, 2214b32e466SDmitry Baryshkov <0x0ae94600 0x280>, 2224b32e466SDmitry Baryshkov <0x0ae94a00 0x1e0>; 2234b32e466SDmitry Baryshkov reg-names = "dsi_phy", 2244b32e466SDmitry Baryshkov "dsi_phy_lane", 2254b32e466SDmitry Baryshkov "dsi_pll"; 2264b32e466SDmitry Baryshkov 2274b32e466SDmitry Baryshkov #clock-cells = <1>; 2284b32e466SDmitry Baryshkov #phy-cells = <0>; 2294b32e466SDmitry Baryshkov 2304b32e466SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2314b32e466SDmitry Baryshkov <&rpmhcc RPMH_CXO_CLK>; 2324b32e466SDmitry Baryshkov clock-names = "iface", "ref"; 2334b32e466SDmitry Baryshkov vdds-supply = <&vreg_dsi_phy>; 2344b32e466SDmitry Baryshkov }; 2354b32e466SDmitry Baryshkov 2364b32e466SDmitry Baryshkov displayport-controller@ae90000 { 2374b32e466SDmitry Baryshkov compatible = "qcom,sc7180-dp"; 2384b32e466SDmitry Baryshkov 2394b32e466SDmitry Baryshkov reg = <0xae90000 0x200>, 2404b32e466SDmitry Baryshkov <0xae90200 0x200>, 2414b32e466SDmitry Baryshkov <0xae90400 0xc00>, 2424b32e466SDmitry Baryshkov <0xae91000 0x400>, 2434b32e466SDmitry Baryshkov <0xae91400 0x400>; 2444b32e466SDmitry Baryshkov 2454b32e466SDmitry Baryshkov interrupt-parent = <&mdss>; 2464b32e466SDmitry Baryshkov interrupts = <12>; 2474b32e466SDmitry Baryshkov 2484b32e466SDmitry Baryshkov clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2494b32e466SDmitry Baryshkov <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2504b32e466SDmitry Baryshkov <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2514b32e466SDmitry Baryshkov <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2524b32e466SDmitry Baryshkov <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2534b32e466SDmitry Baryshkov clock-names = "core_iface", "core_aux", "ctrl_link", 2544b32e466SDmitry Baryshkov "ctrl_link_iface", "stream_pixel"; 2554b32e466SDmitry Baryshkov assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2564b32e466SDmitry Baryshkov <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2574b32e466SDmitry Baryshkov assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; 2584b32e466SDmitry Baryshkov phys = <&dp_phy>; 2594b32e466SDmitry Baryshkov phy-names = "dp"; 2604b32e466SDmitry Baryshkov 2614b32e466SDmitry Baryshkov operating-points-v2 = <&dp_opp_table>; 2624b32e466SDmitry Baryshkov power-domains = <&rpmhpd SC7180_CX>; 2634b32e466SDmitry Baryshkov 2644b32e466SDmitry Baryshkov #sound-dai-cells = <0>; 2654b32e466SDmitry Baryshkov 2664b32e466SDmitry Baryshkov ports { 2674b32e466SDmitry Baryshkov #address-cells = <1>; 2684b32e466SDmitry Baryshkov #size-cells = <0>; 2694b32e466SDmitry Baryshkov port@0 { 2704b32e466SDmitry Baryshkov reg = <0>; 2714b32e466SDmitry Baryshkov dp_in: endpoint { 2724b32e466SDmitry Baryshkov remote-endpoint = <&dpu_intf0_out>; 2734b32e466SDmitry Baryshkov }; 2744b32e466SDmitry Baryshkov }; 2754b32e466SDmitry Baryshkov 2764b32e466SDmitry Baryshkov port@1 { 2774b32e466SDmitry Baryshkov reg = <1>; 2784b32e466SDmitry Baryshkov dp_out: endpoint { }; 2794b32e466SDmitry Baryshkov }; 2804b32e466SDmitry Baryshkov }; 2814b32e466SDmitry Baryshkov 2824b32e466SDmitry Baryshkov dp_opp_table: opp-table { 2834b32e466SDmitry Baryshkov compatible = "operating-points-v2"; 2844b32e466SDmitry Baryshkov 2854b32e466SDmitry Baryshkov opp-160000000 { 2864b32e466SDmitry Baryshkov opp-hz = /bits/ 64 <160000000>; 2874b32e466SDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 2884b32e466SDmitry Baryshkov }; 2894b32e466SDmitry Baryshkov 2904b32e466SDmitry Baryshkov opp-270000000 { 2914b32e466SDmitry Baryshkov opp-hz = /bits/ 64 <270000000>; 2924b32e466SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs>; 2934b32e466SDmitry Baryshkov }; 2944b32e466SDmitry Baryshkov 2954b32e466SDmitry Baryshkov opp-540000000 { 2964b32e466SDmitry Baryshkov opp-hz = /bits/ 64 <540000000>; 2974b32e466SDmitry Baryshkov required-opps = <&rpmhpd_opp_svs_l1>; 2984b32e466SDmitry Baryshkov }; 2994b32e466SDmitry Baryshkov 3004b32e466SDmitry Baryshkov opp-810000000 { 3014b32e466SDmitry Baryshkov opp-hz = /bits/ 64 <810000000>; 3024b32e466SDmitry Baryshkov required-opps = <&rpmhpd_opp_nom>; 3034b32e466SDmitry Baryshkov }; 3044b32e466SDmitry Baryshkov }; 3054b32e466SDmitry Baryshkov }; 306aba04b0dSDmitry Baryshkov }; 307aba04b0dSDmitry Baryshkov... 308