1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI 7nm PHY
8
9maintainers:
10  - Jonathan Marek <jonathan@marek.ca>
11
12allOf:
13  - $ref: dsi-phy-common.yaml#
14
15properties:
16  compatible:
17    oneOf:
18      - const: qcom,dsi-phy-7nm
19      - const: qcom,dsi-phy-7nm-8150
20
21  reg:
22    items:
23      - description: dsi phy register set
24      - description: dsi phy lane register set
25      - description: dsi pll register set
26
27  reg-names:
28    items:
29      - const: dsi_phy
30      - const: dsi_phy_lane
31      - const: dsi_pll
32
33  vdds-supply:
34    description: |
35      Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150)
36
37  phy-type:
38    description: D-PHY (default) or C-PHY mode
39    enum: [ 10, 11 ]
40    default: 10
41
42required:
43  - compatible
44  - reg
45  - reg-names
46  - vdds-supply
47
48unevaluatedProperties: false
49
50examples:
51  - |
52     #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
53     #include <dt-bindings/clock/qcom,rpmh.h>
54
55     dsi-phy@ae94400 {
56         compatible = "qcom,dsi-phy-7nm";
57         reg = <0x0ae94400 0x200>,
58               <0x0ae94600 0x280>,
59               <0x0ae94900 0x260>;
60         reg-names = "dsi_phy",
61                     "dsi_phy_lane",
62                     "dsi_pll";
63
64         #clock-cells = <1>;
65         #phy-cells = <0>;
66
67         vdds-supply = <&vreg_l5a_0p88>;
68         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
69                  <&rpmhcc RPMH_CXO_CLK>;
70         clock-names = "iface", "ref";
71     };
72