1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI controller
8
9maintainers:
10  - Krishna Manikandan <mkrishn@codeaurora.org>
11
12allOf:
13  - $ref: "../dsi-controller.yaml#"
14
15properties:
16  compatible:
17    items:
18      - const: qcom,mdss-dsi-ctrl
19
20  reg:
21    maxItems: 1
22
23  reg-names:
24    const: dsi_ctrl
25
26  interrupts:
27    maxItems: 1
28
29  clocks:
30    items:
31      - description: Display byte clock
32      - description: Display byte interface clock
33      - description: Display pixel clock
34      - description: Display escape clock
35      - description: Display AHB clock
36      - description: Display AXI clock
37
38  clock-names:
39    items:
40      - const: byte
41      - const: byte_intf
42      - const: pixel
43      - const: core
44      - const: iface
45      - const: bus
46
47  phys:
48    maxItems: 1
49
50  phy-names:
51    const: dsi
52
53  "#address-cells": true
54
55  "#size-cells": true
56
57  syscon-sfpb:
58    description: A phandle to mmss_sfpb syscon node (only for DSIv2).
59    $ref: "/schemas/types.yaml#/definitions/phandle"
60
61  qcom,dual-dsi-mode:
62    type: boolean
63    description: |
64      Indicates if the DSI controller is driving a panel which needs
65      2 DSI links.
66
67  assigned-clocks:
68    minItems: 2
69    maxItems: 2
70    description: |
71      Parents of "byte" and "pixel" for the given platform.
72
73  assigned-clock-parents:
74    minItems: 2
75    maxItems: 2
76    description: |
77      The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
78
79  power-domains:
80    maxItems: 1
81
82  operating-points-v2: true
83
84  ports:
85    $ref: "/schemas/graph.yaml#/properties/ports"
86    description: |
87      Contains DSI controller input and output ports as children, each
88      containing one endpoint subnode.
89
90    properties:
91      port@0:
92        $ref: "/schemas/graph.yaml#/$defs/port-base"
93        unevaluatedProperties: false
94        description: |
95          Input endpoints of the controller.
96        properties:
97          endpoint:
98            $ref: /schemas/media/video-interfaces.yaml#
99            unevaluatedProperties: false
100            properties:
101              data-lanes:
102                maxItems: 4
103                minItems: 4
104                items:
105                  enum: [ 0, 1, 2, 3 ]
106
107      port@1:
108        $ref: "/schemas/graph.yaml#/$defs/port-base"
109        unevaluatedProperties: false
110        description: |
111          Output endpoints of the controller.
112        properties:
113          endpoint:
114            $ref: /schemas/media/video-interfaces.yaml#
115            unevaluatedProperties: false
116            properties:
117              data-lanes:
118                maxItems: 4
119                minItems: 4
120                items:
121                  enum: [ 0, 1, 2, 3 ]
122
123    required:
124      - port@0
125      - port@1
126
127required:
128  - compatible
129  - reg
130  - reg-names
131  - interrupts
132  - clocks
133  - clock-names
134  - phys
135  - phy-names
136  - assigned-clocks
137  - assigned-clock-parents
138  - power-domains
139  - operating-points-v2
140  - ports
141
142additionalProperties: false
143
144examples:
145  - |
146     #include <dt-bindings/interrupt-controller/arm-gic.h>
147     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
148     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
149     #include <dt-bindings/power/qcom-rpmpd.h>
150
151     dsi@ae94000 {
152           compatible = "qcom,mdss-dsi-ctrl";
153           reg = <0x0ae94000 0x400>;
154           reg-names = "dsi_ctrl";
155
156           #address-cells = <1>;
157           #size-cells = <0>;
158
159           interrupt-parent = <&mdss>;
160           interrupts = <4>;
161
162           clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
163                    <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
164                    <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
165                    <&dispcc DISP_CC_MDSS_ESC0_CLK>,
166                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
167                    <&dispcc DISP_CC_MDSS_AXI_CLK>;
168           clock-names = "byte",
169                         "byte_intf",
170                         "pixel",
171                         "core",
172                         "iface",
173                         "bus";
174
175           phys = <&dsi0_phy>;
176           phy-names = "dsi";
177
178           assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
179           assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
180
181           power-domains = <&rpmhpd SC7180_CX>;
182           operating-points-v2 = <&dsi_opp_table>;
183
184           ports {
185                  #address-cells = <1>;
186                  #size-cells = <0>;
187
188                  port@0 {
189                          reg = <0>;
190                          dsi0_in: endpoint {
191                                   remote-endpoint = <&dpu_intf1_out>;
192                          };
193                  };
194
195                  port@1 {
196                          reg = <1>;
197                          dsi0_out: endpoint {
198                                   remote-endpoint = <&sn65dsi86_in>;
199                                   data-lanes = <0 1 2 3>;
200                          };
201                  };
202           };
203     };
204...
205