1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI controller
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12allOf:
13  - $ref: "../dsi-controller.yaml#"
14
15properties:
16  compatible:
17    enum:
18      - qcom,mdss-dsi-ctrl
19      - qcom,dsi-ctrl-6g-qcm2290
20
21  reg:
22    maxItems: 1
23
24  reg-names:
25    const: dsi_ctrl
26
27  interrupts:
28    maxItems: 1
29
30  clocks:
31    items:
32      - description: Display byte clock
33      - description: Display byte interface clock
34      - description: Display pixel clock
35      - description: Display escape clock
36      - description: Display AHB clock
37      - description: Display AXI clock
38
39  clock-names:
40    items:
41      - const: byte
42      - const: byte_intf
43      - const: pixel
44      - const: core
45      - const: iface
46      - const: bus
47
48  phys:
49    maxItems: 1
50
51  phy-names:
52    const: dsi
53
54  "#address-cells": true
55
56  "#size-cells": true
57
58  syscon-sfpb:
59    description: A phandle to mmss_sfpb syscon node (only for DSIv2).
60    $ref: "/schemas/types.yaml#/definitions/phandle"
61
62  qcom,dual-dsi-mode:
63    type: boolean
64    description: |
65      Indicates if the DSI controller is driving a panel which needs
66      2 DSI links.
67
68  assigned-clocks:
69    maxItems: 2
70    description: |
71      Parents of "byte" and "pixel" for the given platform.
72
73  assigned-clock-parents:
74    maxItems: 2
75    description: |
76      The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
77
78  power-domains:
79    maxItems: 1
80
81  operating-points-v2: true
82
83  opp-table:
84    type: object
85
86  ports:
87    $ref: "/schemas/graph.yaml#/properties/ports"
88    description: |
89      Contains DSI controller input and output ports as children, each
90      containing one endpoint subnode.
91
92    properties:
93      port@0:
94        $ref: "/schemas/graph.yaml#/$defs/port-base"
95        unevaluatedProperties: false
96        description: |
97          Input endpoints of the controller.
98        properties:
99          endpoint:
100            $ref: /schemas/media/video-interfaces.yaml#
101            unevaluatedProperties: false
102            properties:
103              data-lanes:
104                maxItems: 4
105                minItems: 4
106                items:
107                  enum: [ 0, 1, 2, 3 ]
108
109      port@1:
110        $ref: "/schemas/graph.yaml#/$defs/port-base"
111        unevaluatedProperties: false
112        description: |
113          Output endpoints of the controller.
114        properties:
115          endpoint:
116            $ref: /schemas/media/video-interfaces.yaml#
117            unevaluatedProperties: false
118            properties:
119              data-lanes:
120                maxItems: 4
121                minItems: 4
122                items:
123                  enum: [ 0, 1, 2, 3 ]
124
125    required:
126      - port@0
127      - port@1
128
129required:
130  - compatible
131  - reg
132  - reg-names
133  - interrupts
134  - clocks
135  - clock-names
136  - phys
137  - phy-names
138  - assigned-clocks
139  - assigned-clock-parents
140  - power-domains
141  - operating-points-v2
142  - ports
143
144additionalProperties: false
145
146examples:
147  - |
148     #include <dt-bindings/interrupt-controller/arm-gic.h>
149     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
150     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
151     #include <dt-bindings/power/qcom-rpmpd.h>
152
153     dsi@ae94000 {
154           compatible = "qcom,mdss-dsi-ctrl";
155           reg = <0x0ae94000 0x400>;
156           reg-names = "dsi_ctrl";
157
158           #address-cells = <1>;
159           #size-cells = <0>;
160
161           interrupt-parent = <&mdss>;
162           interrupts = <4>;
163
164           clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
165                    <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
166                    <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
167                    <&dispcc DISP_CC_MDSS_ESC0_CLK>,
168                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
169                    <&dispcc DISP_CC_MDSS_AXI_CLK>;
170           clock-names = "byte",
171                         "byte_intf",
172                         "pixel",
173                         "core",
174                         "iface",
175                         "bus";
176
177           phys = <&dsi0_phy>;
178           phy-names = "dsi";
179
180           assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
181           assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
182
183           power-domains = <&rpmhpd SC7180_CX>;
184           operating-points-v2 = <&dsi_opp_table>;
185
186           ports {
187                  #address-cells = <1>;
188                  #size-cells = <0>;
189
190                  port@0 {
191                          reg = <0>;
192                          dsi0_in: endpoint {
193                                   remote-endpoint = <&dpu_intf1_out>;
194                          };
195                  };
196
197                  port@1 {
198                          reg = <1>;
199                          dsi0_out: endpoint {
200                                   remote-endpoint = <&sn65dsi86_in>;
201                                   data-lanes = <0 1 2 3>;
202                          };
203                  };
204           };
205     };
206...
207