1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI controller
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12allOf:
13  - $ref: "../dsi-controller.yaml#"
14
15properties:
16  compatible:
17    enum:
18      - qcom,mdss-dsi-ctrl
19      - qcom,dsi-ctrl-6g-qcm2290
20
21  reg:
22    maxItems: 1
23
24  reg-names:
25    const: dsi_ctrl
26
27  interrupts:
28    maxItems: 1
29
30  clocks:
31    items:
32      - description: Display byte clock
33      - description: Display byte interface clock
34      - description: Display pixel clock
35      - description: Display core clock
36      - description: Display AHB clock
37      - description: Display AXI clock
38
39  clock-names:
40    items:
41      - const: byte
42      - const: byte_intf
43      - const: pixel
44      - const: core
45      - const: iface
46      - const: bus
47
48  phys:
49    maxItems: 1
50
51  phy-names:
52    deprecated: true
53    const: dsi
54
55  "#address-cells": true
56
57  "#size-cells": true
58
59  syscon-sfpb:
60    description: A phandle to mmss_sfpb syscon node (only for DSIv2).
61    $ref: "/schemas/types.yaml#/definitions/phandle"
62
63  qcom,dual-dsi-mode:
64    type: boolean
65    description: |
66      Indicates if the DSI controller is driving a panel which needs
67      2 DSI links.
68
69  assigned-clocks:
70    maxItems: 2
71    description: |
72      Parents of "byte" and "pixel" for the given platform.
73
74  assigned-clock-parents:
75    maxItems: 2
76    description: |
77      The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
78
79  power-domains:
80    maxItems: 1
81
82  operating-points-v2: true
83
84  opp-table:
85    type: object
86
87  ports:
88    $ref: "/schemas/graph.yaml#/properties/ports"
89    description: |
90      Contains DSI controller input and output ports as children, each
91      containing one endpoint subnode.
92
93    properties:
94      port@0:
95        $ref: "/schemas/graph.yaml#/$defs/port-base"
96        unevaluatedProperties: false
97        description: |
98          Input endpoints of the controller.
99        properties:
100          endpoint:
101            $ref: /schemas/media/video-interfaces.yaml#
102            unevaluatedProperties: false
103            properties:
104              data-lanes:
105                maxItems: 4
106                minItems: 4
107                items:
108                  enum: [ 0, 1, 2, 3 ]
109
110      port@1:
111        $ref: "/schemas/graph.yaml#/$defs/port-base"
112        unevaluatedProperties: false
113        description: |
114          Output endpoints of the controller.
115        properties:
116          endpoint:
117            $ref: /schemas/media/video-interfaces.yaml#
118            unevaluatedProperties: false
119            properties:
120              data-lanes:
121                maxItems: 4
122                minItems: 4
123                items:
124                  enum: [ 0, 1, 2, 3 ]
125
126    required:
127      - port@0
128      - port@1
129
130  vdd-supply:
131    description:
132      VDD regulator
133
134  vddio-supply:
135    description:
136      VDD-IO regulator
137
138  vdda-supply:
139    description:
140      VDDA regulator
141
142required:
143  - compatible
144  - reg
145  - reg-names
146  - interrupts
147  - clocks
148  - clock-names
149  - phys
150  - assigned-clocks
151  - assigned-clock-parents
152  - ports
153
154additionalProperties: false
155
156examples:
157  - |
158     #include <dt-bindings/interrupt-controller/arm-gic.h>
159     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
160     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
161     #include <dt-bindings/power/qcom-rpmpd.h>
162
163     dsi@ae94000 {
164           compatible = "qcom,mdss-dsi-ctrl";
165           reg = <0x0ae94000 0x400>;
166           reg-names = "dsi_ctrl";
167
168           #address-cells = <1>;
169           #size-cells = <0>;
170
171           interrupt-parent = <&mdss>;
172           interrupts = <4>;
173
174           clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
175                    <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
176                    <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
177                    <&dispcc DISP_CC_MDSS_ESC0_CLK>,
178                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
179                    <&dispcc DISP_CC_MDSS_AXI_CLK>;
180           clock-names = "byte",
181                         "byte_intf",
182                         "pixel",
183                         "core",
184                         "iface",
185                         "bus";
186
187           phys = <&dsi0_phy>;
188           phy-names = "dsi";
189
190           assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
191           assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
192
193           power-domains = <&rpmhpd SC7180_CX>;
194           operating-points-v2 = <&dsi_opp_table>;
195
196           ports {
197                  #address-cells = <1>;
198                  #size-cells = <0>;
199
200                  port@0 {
201                          reg = <0>;
202                          dsi0_in: endpoint {
203                                   remote-endpoint = <&dpu_intf1_out>;
204                          };
205                  };
206
207                  port@1 {
208                          reg = <1>;
209                          dsi0_out: endpoint {
210                                   remote-endpoint = <&sn65dsi86_in>;
211                                   data-lanes = <0 1 2 3>;
212                          };
213                  };
214           };
215     };
216...
217