1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DSI controller 8 9maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - qcom,apq8064-dsi-ctrl 18 - qcom,msm8916-dsi-ctrl 19 - qcom,msm8953-dsi-ctrl 20 - qcom,msm8974-dsi-ctrl 21 - qcom,msm8996-dsi-ctrl 22 - qcom,msm8998-dsi-ctrl 23 - qcom,qcm2290-dsi-ctrl 24 - qcom,sc7180-dsi-ctrl 25 - qcom,sc7280-dsi-ctrl 26 - qcom,sdm660-dsi-ctrl 27 - qcom,sdm845-dsi-ctrl 28 - qcom,sm8150-dsi-ctrl 29 - qcom,sm8250-dsi-ctrl 30 - qcom,sm8350-dsi-ctrl 31 - qcom,sm8450-dsi-ctrl 32 - qcom,sm8550-dsi-ctrl 33 - const: qcom,mdss-dsi-ctrl 34 - items: 35 - enum: 36 - dsi-ctrl-6g-qcm2290 37 - const: qcom,mdss-dsi-ctrl 38 deprecated: true 39 40 reg: 41 maxItems: 1 42 43 reg-names: 44 const: dsi_ctrl 45 46 interrupts: 47 maxItems: 1 48 49 clocks: 50 description: | 51 Several clocks are used, depending on the variant. Typical ones are:: 52 - bus:: Display AHB clock. 53 - byte:: Display byte clock. 54 - byte_intf:: Display byte interface clock. 55 - core:: Display core clock. 56 - core_mss:: Core MultiMedia SubSystem clock. 57 - iface:: Display AXI clock. 58 - mdp_core:: MDP Core clock. 59 - mnoc:: MNOC clock 60 - pixel:: Display pixel clock. 61 minItems: 3 62 maxItems: 9 63 64 clock-names: 65 minItems: 3 66 maxItems: 9 67 68 phys: 69 maxItems: 1 70 71 phy-names: 72 deprecated: true 73 const: dsi 74 75 syscon-sfpb: 76 description: A phandle to mmss_sfpb syscon node (only for DSIv2). 77 $ref: "/schemas/types.yaml#/definitions/phandle" 78 79 qcom,dual-dsi-mode: 80 type: boolean 81 description: | 82 Indicates if the DSI controller is driving a panel which needs 83 2 DSI links. 84 85 assigned-clocks: 86 maxItems: 2 87 description: | 88 Parents of "byte" and "pixel" for the given platform. 89 90 assigned-clock-parents: 91 maxItems: 2 92 description: | 93 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. 94 95 power-domains: 96 maxItems: 1 97 98 operating-points-v2: true 99 100 opp-table: 101 type: object 102 103 ports: 104 $ref: "/schemas/graph.yaml#/properties/ports" 105 description: | 106 Contains DSI controller input and output ports as children, each 107 containing one endpoint subnode. 108 109 properties: 110 port@0: 111 $ref: "/schemas/graph.yaml#/$defs/port-base" 112 unevaluatedProperties: false 113 description: | 114 Input endpoints of the controller. 115 properties: 116 endpoint: 117 $ref: /schemas/media/video-interfaces.yaml# 118 unevaluatedProperties: false 119 properties: 120 data-lanes: 121 maxItems: 4 122 minItems: 4 123 items: 124 enum: [ 0, 1, 2, 3 ] 125 126 port@1: 127 $ref: "/schemas/graph.yaml#/$defs/port-base" 128 unevaluatedProperties: false 129 description: | 130 Output endpoints of the controller. 131 properties: 132 endpoint: 133 $ref: /schemas/media/video-interfaces.yaml# 134 unevaluatedProperties: false 135 properties: 136 data-lanes: 137 maxItems: 4 138 minItems: 4 139 items: 140 enum: [ 0, 1, 2, 3 ] 141 142 required: 143 - port@0 144 - port@1 145 146 vdd-supply: 147 description: 148 VDD regulator 149 150 vddio-supply: 151 description: 152 VDD-IO regulator 153 154 vdda-supply: 155 description: 156 VDDA regulator 157 158required: 159 - compatible 160 - reg 161 - reg-names 162 - interrupts 163 - clocks 164 - clock-names 165 - phys 166 - assigned-clocks 167 - assigned-clock-parents 168 - ports 169 170allOf: 171 - $ref: ../dsi-controller.yaml# 172 - if: 173 properties: 174 compatible: 175 contains: 176 enum: 177 - qcom,apq8064-dsi-ctrl 178 then: 179 properties: 180 clocks: 181 maxItems: 7 182 clock-names: 183 items: 184 - const: iface 185 - const: bus 186 - const: core_mmss 187 - const: src 188 - const: byte 189 - const: pixel 190 - const: core 191 192 - if: 193 properties: 194 compatible: 195 contains: 196 enum: 197 - qcom,msm8916-dsi-ctrl 198 then: 199 properties: 200 clocks: 201 maxItems: 6 202 clock-names: 203 items: 204 - const: mdp_core 205 - const: iface 206 - const: bus 207 - const: byte 208 - const: pixel 209 - const: core 210 211 - if: 212 properties: 213 compatible: 214 contains: 215 enum: 216 - qcom,msm8953-dsi-ctrl 217 then: 218 properties: 219 clocks: 220 maxItems: 6 221 clock-names: 222 items: 223 - const: mdp_core 224 - const: iface 225 - const: bus 226 - const: byte 227 - const: pixel 228 - const: core 229 230 - if: 231 properties: 232 compatible: 233 contains: 234 enum: 235 - qcom,msm8974-dsi-ctrl 236 then: 237 properties: 238 clocks: 239 maxItems: 7 240 clock-names: 241 items: 242 - const: mdp_core 243 - const: iface 244 - const: bus 245 - const: byte 246 - const: pixel 247 - const: core 248 - const: core_mmss 249 250 - if: 251 properties: 252 compatible: 253 contains: 254 enum: 255 - qcom,msm8996-dsi-ctrl 256 then: 257 properties: 258 clocks: 259 maxItems: 7 260 clock-names: 261 items: 262 - const: mdp_core 263 - const: byte 264 - const: iface 265 - const: bus 266 - const: core_mmss 267 - const: pixel 268 - const: core 269 270 - if: 271 properties: 272 compatible: 273 contains: 274 enum: 275 - qcom,msm8998-dsi-ctrl 276 then: 277 properties: 278 clocks: 279 maxItems: 6 280 clock-names: 281 items: 282 - const: byte 283 - const: byte_intf 284 - const: pixel 285 - const: core 286 - const: iface 287 - const: bus 288 289 - if: 290 properties: 291 compatible: 292 contains: 293 enum: 294 - qcom,sc7180-dsi-ctrl 295 - qcom,sc7280-dsi-ctrl 296 - qcom,sm8150-dsi-ctrl 297 - qcom,sm8250-dsi-ctrl 298 - qcom,sm8350-dsi-ctrl 299 - qcom,sm8450-dsi-ctrl 300 - qcom,sm8550-dsi-ctrl 301 then: 302 properties: 303 clocks: 304 maxItems: 6 305 clock-names: 306 items: 307 - const: byte 308 - const: byte_intf 309 - const: pixel 310 - const: core 311 - const: iface 312 - const: bus 313 314 - if: 315 properties: 316 compatible: 317 contains: 318 enum: 319 - qcom,sdm660-dsi-ctrl 320 then: 321 properties: 322 clocks: 323 maxItems: 9 324 clock-names: 325 items: 326 - const: mdp_core 327 - const: byte 328 - const: byte_intf 329 - const: mnoc 330 - const: iface 331 - const: bus 332 - const: core_mmss 333 - const: pixel 334 - const: core 335 336 - if: 337 properties: 338 compatible: 339 contains: 340 enum: 341 - qcom,sdm845-dsi-ctrl 342 then: 343 properties: 344 clocks: 345 maxItems: 6 346 clock-names: 347 items: 348 - const: byte 349 - const: byte_intf 350 - const: pixel 351 - const: core 352 - const: iface 353 - const: bus 354 355unevaluatedProperties: false 356 357examples: 358 - | 359 #include <dt-bindings/interrupt-controller/arm-gic.h> 360 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 361 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 362 #include <dt-bindings/power/qcom-rpmpd.h> 363 364 dsi@ae94000 { 365 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 366 reg = <0x0ae94000 0x400>; 367 reg-names = "dsi_ctrl"; 368 369 #address-cells = <1>; 370 #size-cells = <0>; 371 372 interrupt-parent = <&mdss>; 373 interrupts = <4>; 374 375 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 376 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 377 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 378 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 379 <&dispcc DISP_CC_MDSS_AHB_CLK>, 380 <&dispcc DISP_CC_MDSS_AXI_CLK>; 381 clock-names = "byte", 382 "byte_intf", 383 "pixel", 384 "core", 385 "iface", 386 "bus"; 387 388 phys = <&dsi0_phy>; 389 phy-names = "dsi"; 390 391 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 392 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 393 394 power-domains = <&rpmhpd SC7180_CX>; 395 operating-points-v2 = <&dsi_opp_table>; 396 397 ports { 398 #address-cells = <1>; 399 #size-cells = <0>; 400 401 port@0 { 402 reg = <0>; 403 dsi0_in: endpoint { 404 remote-endpoint = <&dpu_intf1_out>; 405 }; 406 }; 407 408 port@1 { 409 reg = <1>; 410 dsi0_out: endpoint { 411 remote-endpoint = <&sn65dsi86_in>; 412 data-lanes = <0 1 2 3>; 413 }; 414 }; 415 }; 416 }; 417... 418