1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI controller
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12allOf:
13  - $ref: "../dsi-controller.yaml#"
14
15properties:
16  compatible:
17    enum:
18      - qcom,mdss-dsi-ctrl
19      - qcom,dsi-ctrl-6g-qcm2290
20
21  reg:
22    maxItems: 1
23
24  reg-names:
25    const: dsi_ctrl
26
27  interrupts:
28    maxItems: 1
29
30  clocks:
31    items:
32      - description: Display byte clock
33      - description: Display byte interface clock
34      - description: Display pixel clock
35      - description: Display core clock
36      - description: Display AHB clock
37      - description: Display AXI clock
38
39  clock-names:
40    items:
41      - const: byte
42      - const: byte_intf
43      - const: pixel
44      - const: core
45      - const: iface
46      - const: bus
47
48  phys:
49    maxItems: 1
50
51  phy-names:
52    deprecated: true
53    const: dsi
54
55  "#address-cells": true
56
57  "#size-cells": true
58
59  syscon-sfpb:
60    description: A phandle to mmss_sfpb syscon node (only for DSIv2).
61    $ref: "/schemas/types.yaml#/definitions/phandle"
62
63  qcom,dual-dsi-mode:
64    type: boolean
65    description: |
66      Indicates if the DSI controller is driving a panel which needs
67      2 DSI links.
68
69  assigned-clocks:
70    maxItems: 2
71    description: |
72      Parents of "byte" and "pixel" for the given platform.
73
74  assigned-clock-parents:
75    maxItems: 2
76    description: |
77      The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
78
79  power-domains:
80    maxItems: 1
81
82  operating-points-v2: true
83
84  opp-table:
85    type: object
86
87  ports:
88    $ref: "/schemas/graph.yaml#/properties/ports"
89    description: |
90      Contains DSI controller input and output ports as children, each
91      containing one endpoint subnode.
92
93    properties:
94      port@0:
95        $ref: "/schemas/graph.yaml#/$defs/port-base"
96        unevaluatedProperties: false
97        description: |
98          Input endpoints of the controller.
99        properties:
100          endpoint:
101            $ref: /schemas/media/video-interfaces.yaml#
102            unevaluatedProperties: false
103            properties:
104              data-lanes:
105                maxItems: 4
106                minItems: 4
107                items:
108                  enum: [ 0, 1, 2, 3 ]
109
110      port@1:
111        $ref: "/schemas/graph.yaml#/$defs/port-base"
112        unevaluatedProperties: false
113        description: |
114          Output endpoints of the controller.
115        properties:
116          endpoint:
117            $ref: /schemas/media/video-interfaces.yaml#
118            unevaluatedProperties: false
119            properties:
120              data-lanes:
121                maxItems: 4
122                minItems: 4
123                items:
124                  enum: [ 0, 1, 2, 3 ]
125
126    required:
127      - port@0
128      - port@1
129
130required:
131  - compatible
132  - reg
133  - reg-names
134  - interrupts
135  - clocks
136  - clock-names
137  - phys
138  - assigned-clocks
139  - assigned-clock-parents
140  - ports
141
142additionalProperties: false
143
144examples:
145  - |
146     #include <dt-bindings/interrupt-controller/arm-gic.h>
147     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
148     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
149     #include <dt-bindings/power/qcom-rpmpd.h>
150
151     dsi@ae94000 {
152           compatible = "qcom,mdss-dsi-ctrl";
153           reg = <0x0ae94000 0x400>;
154           reg-names = "dsi_ctrl";
155
156           #address-cells = <1>;
157           #size-cells = <0>;
158
159           interrupt-parent = <&mdss>;
160           interrupts = <4>;
161
162           clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
163                    <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
164                    <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
165                    <&dispcc DISP_CC_MDSS_ESC0_CLK>,
166                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
167                    <&dispcc DISP_CC_MDSS_AXI_CLK>;
168           clock-names = "byte",
169                         "byte_intf",
170                         "pixel",
171                         "core",
172                         "iface",
173                         "bus";
174
175           phys = <&dsi0_phy>;
176           phy-names = "dsi";
177
178           assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
179           assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
180
181           power-domains = <&rpmhpd SC7180_CX>;
182           operating-points-v2 = <&dsi_opp_table>;
183
184           ports {
185                  #address-cells = <1>;
186                  #size-cells = <0>;
187
188                  port@0 {
189                          reg = <0>;
190                          dsi0_in: endpoint {
191                                   remote-endpoint = <&dpu_intf1_out>;
192                          };
193                  };
194
195                  port@1 {
196                          reg = <1>;
197                          dsi0_out: endpoint {
198                                   remote-endpoint = <&sn65dsi86_in>;
199                                   data-lanes = <0 1 2 3>;
200                          };
201                  };
202           };
203     };
204...
205