1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI controller
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12properties:
13  compatible:
14    oneOf:
15      - items:
16          - enum:
17              - qcom,apq8064-dsi-ctrl
18              - qcom,msm8916-dsi-ctrl
19              - qcom,msm8953-dsi-ctrl
20              - qcom,msm8974-dsi-ctrl
21              - qcom,msm8996-dsi-ctrl
22              - qcom,msm8998-dsi-ctrl
23              - qcom,qcm2290-dsi-ctrl
24              - qcom,sc7180-dsi-ctrl
25              - qcom,sc7280-dsi-ctrl
26              - qcom,sdm660-dsi-ctrl
27              - qcom,sdm845-dsi-ctrl
28              - qcom,sm8150-dsi-ctrl
29              - qcom,sm8250-dsi-ctrl
30              - qcom,sm8350-dsi-ctrl
31              - qcom,sm8450-dsi-ctrl
32              - qcom,sm8550-dsi-ctrl
33          - const: qcom,mdss-dsi-ctrl
34      - enum:
35          - qcom,dsi-ctrl-6g-qcm2290
36          - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible
37        deprecated: true
38
39  reg:
40    maxItems: 1
41
42  reg-names:
43    const: dsi_ctrl
44
45  interrupts:
46    maxItems: 1
47
48  clocks:
49    description: |
50      Several clocks are used, depending on the variant. Typical ones are::
51       - bus:: Display AHB clock.
52       - byte:: Display byte clock.
53       - byte_intf:: Display byte interface clock.
54       - core:: Display core clock.
55       - core_mss:: Core MultiMedia SubSystem clock.
56       - iface:: Display AXI clock.
57       - mdp_core:: MDP Core clock.
58       - mnoc:: MNOC clock
59       - pixel:: Display pixel clock.
60    minItems: 3
61    maxItems: 9
62
63  clock-names:
64    minItems: 3
65    maxItems: 9
66
67  phys:
68    maxItems: 1
69
70  phy-names:
71    deprecated: true
72    const: dsi
73
74  syscon-sfpb:
75    description: A phandle to mmss_sfpb syscon node (only for DSIv2).
76    $ref: "/schemas/types.yaml#/definitions/phandle"
77
78  qcom,dual-dsi-mode:
79    type: boolean
80    description: |
81      Indicates if the DSI controller is driving a panel which needs
82      2 DSI links.
83
84  assigned-clocks:
85    minItems: 2
86    maxItems: 4
87    description: |
88      Parents of "byte" and "pixel" for the given platform.
89      For DSIv2 platforms this should contain "byte", "esc", "src" and
90      "pixel_src" clocks.
91
92  assigned-clock-parents:
93    minItems: 2
94    maxItems: 4
95    description: |
96      The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
97
98  power-domains:
99    maxItems: 1
100
101  operating-points-v2: true
102
103  opp-table:
104    type: object
105
106  ports:
107    $ref: "/schemas/graph.yaml#/properties/ports"
108    description: |
109      Contains DSI controller input and output ports as children, each
110      containing one endpoint subnode.
111
112    properties:
113      port@0:
114        $ref: "/schemas/graph.yaml#/$defs/port-base"
115        unevaluatedProperties: false
116        description: |
117          Input endpoints of the controller.
118        properties:
119          endpoint:
120            $ref: /schemas/media/video-interfaces.yaml#
121            unevaluatedProperties: false
122            properties:
123              data-lanes:
124                maxItems: 4
125                minItems: 1
126                items:
127                  enum: [ 0, 1, 2, 3 ]
128
129      port@1:
130        $ref: "/schemas/graph.yaml#/$defs/port-base"
131        unevaluatedProperties: false
132        description: |
133          Output endpoints of the controller.
134        properties:
135          endpoint:
136            $ref: /schemas/media/video-interfaces.yaml#
137            unevaluatedProperties: false
138            properties:
139              data-lanes:
140                maxItems: 4
141                minItems: 1
142                items:
143                  enum: [ 0, 1, 2, 3 ]
144
145    required:
146      - port@0
147      - port@1
148
149  avdd-supply:
150    description:
151      Phandle to vdd regulator device node
152
153  vcca-supply:
154    description:
155      Phandle to vdd regulator device node
156
157  vdd-supply:
158    description:
159      VDD regulator
160
161  vddio-supply:
162    description:
163      VDD-IO regulator
164
165  vdda-supply:
166    description:
167      VDDA regulator
168
169required:
170  - compatible
171  - reg
172  - reg-names
173  - interrupts
174  - clocks
175  - clock-names
176  - phys
177  - assigned-clocks
178  - assigned-clock-parents
179  - ports
180
181allOf:
182  - $ref: ../dsi-controller.yaml#
183  - if:
184      properties:
185        compatible:
186          contains:
187            enum:
188              - qcom,apq8064-dsi-ctrl
189    then:
190      properties:
191        clocks:
192          maxItems: 7
193        clock-names:
194          items:
195            - const: iface
196            - const: bus
197            - const: core_mmss
198            - const: src
199            - const: byte
200            - const: pixel
201            - const: core
202
203  - if:
204      properties:
205        compatible:
206          contains:
207            enum:
208              - qcom,msm8916-dsi-ctrl
209    then:
210      properties:
211        clocks:
212          maxItems: 6
213        clock-names:
214          items:
215            - const: mdp_core
216            - const: iface
217            - const: bus
218            - const: byte
219            - const: pixel
220            - const: core
221
222  - if:
223      properties:
224        compatible:
225          contains:
226            enum:
227              - qcom,msm8953-dsi-ctrl
228    then:
229      properties:
230        clocks:
231          maxItems: 6
232        clock-names:
233          items:
234            - const: mdp_core
235            - const: iface
236            - const: bus
237            - const: byte
238            - const: pixel
239            - const: core
240
241  - if:
242      properties:
243        compatible:
244          contains:
245            enum:
246              - qcom,msm8974-dsi-ctrl
247    then:
248      properties:
249        clocks:
250          maxItems: 7
251        clock-names:
252          items:
253            - const: mdp_core
254            - const: iface
255            - const: bus
256            - const: byte
257            - const: pixel
258            - const: core
259            - const: core_mmss
260
261  - if:
262      properties:
263        compatible:
264          contains:
265            enum:
266              - qcom,msm8996-dsi-ctrl
267    then:
268      properties:
269        clocks:
270          maxItems: 7
271        clock-names:
272          items:
273            - const: mdp_core
274            - const: byte
275            - const: iface
276            - const: bus
277            - const: core_mmss
278            - const: pixel
279            - const: core
280
281  - if:
282      properties:
283        compatible:
284          contains:
285            enum:
286              - qcom,msm8998-dsi-ctrl
287    then:
288      properties:
289        clocks:
290          maxItems: 6
291        clock-names:
292          items:
293            - const: byte
294            - const: byte_intf
295            - const: pixel
296            - const: core
297            - const: iface
298            - const: bus
299
300  - if:
301      properties:
302        compatible:
303          contains:
304            enum:
305              - qcom,sc7180-dsi-ctrl
306              - qcom,sc7280-dsi-ctrl
307              - qcom,sm8150-dsi-ctrl
308              - qcom,sm8250-dsi-ctrl
309              - qcom,sm8350-dsi-ctrl
310              - qcom,sm8450-dsi-ctrl
311              - qcom,sm8550-dsi-ctrl
312    then:
313      properties:
314        clocks:
315          maxItems: 6
316        clock-names:
317          items:
318            - const: byte
319            - const: byte_intf
320            - const: pixel
321            - const: core
322            - const: iface
323            - const: bus
324
325  - if:
326      properties:
327        compatible:
328          contains:
329            enum:
330              - qcom,sdm660-dsi-ctrl
331    then:
332      properties:
333        clocks:
334          maxItems: 9
335        clock-names:
336          items:
337            - const: mdp_core
338            - const: byte
339            - const: byte_intf
340            - const: mnoc
341            - const: iface
342            - const: bus
343            - const: core_mmss
344            - const: pixel
345            - const: core
346
347  - if:
348      properties:
349        compatible:
350          contains:
351            enum:
352              - qcom,sdm845-dsi-ctrl
353    then:
354      properties:
355        clocks:
356          maxItems: 6
357        clock-names:
358          items:
359            - const: byte
360            - const: byte_intf
361            - const: pixel
362            - const: core
363            - const: iface
364            - const: bus
365
366unevaluatedProperties: false
367
368examples:
369  - |
370     #include <dt-bindings/interrupt-controller/arm-gic.h>
371     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
372     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
373     #include <dt-bindings/power/qcom-rpmpd.h>
374
375     dsi@ae94000 {
376           compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
377           reg = <0x0ae94000 0x400>;
378           reg-names = "dsi_ctrl";
379
380           #address-cells = <1>;
381           #size-cells = <0>;
382
383           interrupt-parent = <&mdss>;
384           interrupts = <4>;
385
386           clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
387                    <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
388                    <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
389                    <&dispcc DISP_CC_MDSS_ESC0_CLK>,
390                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
391                    <&dispcc DISP_CC_MDSS_AXI_CLK>;
392           clock-names = "byte",
393                         "byte_intf",
394                         "pixel",
395                         "core",
396                         "iface",
397                         "bus";
398
399           phys = <&dsi0_phy>;
400           phy-names = "dsi";
401
402           assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
403           assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
404
405           power-domains = <&rpmhpd SC7180_CX>;
406           operating-points-v2 = <&dsi_opp_table>;
407
408           ports {
409                  #address-cells = <1>;
410                  #size-cells = <0>;
411
412                  port@0 {
413                          reg = <0>;
414                          dsi0_in: endpoint {
415                                   remote-endpoint = <&dpu_intf1_out>;
416                          };
417                  };
418
419                  port@1 {
420                          reg = <1>;
421                          dsi0_out: endpoint {
422                                   remote-endpoint = <&sn65dsi86_in>;
423                                   data-lanes = <0 1 2 3>;
424                          };
425                  };
426           };
427     };
428...
429