1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI controller
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12properties:
13  compatible:
14    oneOf:
15      - items:
16          - enum:
17              - qcom,apq8064-dsi-ctrl
18              - qcom,msm8916-dsi-ctrl
19              - qcom,msm8953-dsi-ctrl
20              - qcom,msm8974-dsi-ctrl
21              - qcom,msm8996-dsi-ctrl
22              - qcom,msm8998-dsi-ctrl
23              - qcom,qcm2290-dsi-ctrl
24              - qcom,sc7180-dsi-ctrl
25              - qcom,sc7280-dsi-ctrl
26              - qcom,sdm660-dsi-ctrl
27              - qcom,sdm845-dsi-ctrl
28              - qcom,sm8150-dsi-ctrl
29              - qcom,sm8250-dsi-ctrl
30              - qcom,sm8350-dsi-ctrl
31              - qcom,sm8450-dsi-ctrl
32              - qcom,sm8550-dsi-ctrl
33          - const: qcom,mdss-dsi-ctrl
34      - items:
35          - enum:
36              - dsi-ctrl-6g-qcm2290
37          - const: qcom,mdss-dsi-ctrl
38        deprecated: true
39
40  reg:
41    maxItems: 1
42
43  reg-names:
44    const: dsi_ctrl
45
46  interrupts:
47    maxItems: 1
48
49  clocks:
50    description: |
51      Several clocks are used, depending on the variant. Typical ones are::
52       - bus:: Display AHB clock.
53       - byte:: Display byte clock.
54       - byte_intf:: Display byte interface clock.
55       - core:: Display core clock.
56       - core_mss:: Core MultiMedia SubSystem clock.
57       - iface:: Display AXI clock.
58       - mdp_core:: MDP Core clock.
59       - mnoc:: MNOC clock
60       - pixel:: Display pixel clock.
61    minItems: 3
62    maxItems: 9
63
64  clock-names:
65    minItems: 3
66    maxItems: 9
67
68  phys:
69    maxItems: 1
70
71  phy-names:
72    deprecated: true
73    const: dsi
74
75  syscon-sfpb:
76    description: A phandle to mmss_sfpb syscon node (only for DSIv2).
77    $ref: "/schemas/types.yaml#/definitions/phandle"
78
79  qcom,dual-dsi-mode:
80    type: boolean
81    description: |
82      Indicates if the DSI controller is driving a panel which needs
83      2 DSI links.
84
85  assigned-clocks:
86    minItems: 2
87    maxItems: 4
88    description: |
89      Parents of "byte" and "pixel" for the given platform.
90      For DSIv2 platforms this should contain "byte", "esc", "src" and
91      "pixel_src" clocks.
92
93  assigned-clock-parents:
94    minItems: 2
95    maxItems: 4
96    description: |
97      The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
98
99  power-domains:
100    maxItems: 1
101
102  operating-points-v2: true
103
104  opp-table:
105    type: object
106
107  ports:
108    $ref: "/schemas/graph.yaml#/properties/ports"
109    description: |
110      Contains DSI controller input and output ports as children, each
111      containing one endpoint subnode.
112
113    properties:
114      port@0:
115        $ref: "/schemas/graph.yaml#/$defs/port-base"
116        unevaluatedProperties: false
117        description: |
118          Input endpoints of the controller.
119        properties:
120          endpoint:
121            $ref: /schemas/media/video-interfaces.yaml#
122            unevaluatedProperties: false
123            properties:
124              data-lanes:
125                maxItems: 4
126                minItems: 4
127                items:
128                  enum: [ 0, 1, 2, 3 ]
129
130      port@1:
131        $ref: "/schemas/graph.yaml#/$defs/port-base"
132        unevaluatedProperties: false
133        description: |
134          Output endpoints of the controller.
135        properties:
136          endpoint:
137            $ref: /schemas/media/video-interfaces.yaml#
138            unevaluatedProperties: false
139            properties:
140              data-lanes:
141                maxItems: 4
142                minItems: 4
143                items:
144                  enum: [ 0, 1, 2, 3 ]
145
146    required:
147      - port@0
148      - port@1
149
150  vdd-supply:
151    description:
152      VDD regulator
153
154  vddio-supply:
155    description:
156      VDD-IO regulator
157
158  vdda-supply:
159    description:
160      VDDA regulator
161
162required:
163  - compatible
164  - reg
165  - reg-names
166  - interrupts
167  - clocks
168  - clock-names
169  - phys
170  - assigned-clocks
171  - assigned-clock-parents
172  - ports
173
174allOf:
175  - $ref: ../dsi-controller.yaml#
176  - if:
177      properties:
178        compatible:
179          contains:
180            enum:
181              - qcom,apq8064-dsi-ctrl
182    then:
183      properties:
184        clocks:
185          maxItems: 7
186        clock-names:
187          items:
188            - const: iface
189            - const: bus
190            - const: core_mmss
191            - const: src
192            - const: byte
193            - const: pixel
194            - const: core
195
196  - if:
197      properties:
198        compatible:
199          contains:
200            enum:
201              - qcom,msm8916-dsi-ctrl
202    then:
203      properties:
204        clocks:
205          maxItems: 6
206        clock-names:
207          items:
208            - const: mdp_core
209            - const: iface
210            - const: bus
211            - const: byte
212            - const: pixel
213            - const: core
214
215  - if:
216      properties:
217        compatible:
218          contains:
219            enum:
220              - qcom,msm8953-dsi-ctrl
221    then:
222      properties:
223        clocks:
224          maxItems: 6
225        clock-names:
226          items:
227            - const: mdp_core
228            - const: iface
229            - const: bus
230            - const: byte
231            - const: pixel
232            - const: core
233
234  - if:
235      properties:
236        compatible:
237          contains:
238            enum:
239              - qcom,msm8974-dsi-ctrl
240    then:
241      properties:
242        clocks:
243          maxItems: 7
244        clock-names:
245          items:
246            - const: mdp_core
247            - const: iface
248            - const: bus
249            - const: byte
250            - const: pixel
251            - const: core
252            - const: core_mmss
253
254  - if:
255      properties:
256        compatible:
257          contains:
258            enum:
259              - qcom,msm8996-dsi-ctrl
260    then:
261      properties:
262        clocks:
263          maxItems: 7
264        clock-names:
265          items:
266            - const: mdp_core
267            - const: byte
268            - const: iface
269            - const: bus
270            - const: core_mmss
271            - const: pixel
272            - const: core
273
274  - if:
275      properties:
276        compatible:
277          contains:
278            enum:
279              - qcom,msm8998-dsi-ctrl
280    then:
281      properties:
282        clocks:
283          maxItems: 6
284        clock-names:
285          items:
286            - const: byte
287            - const: byte_intf
288            - const: pixel
289            - const: core
290            - const: iface
291            - const: bus
292
293  - if:
294      properties:
295        compatible:
296          contains:
297            enum:
298              - qcom,sc7180-dsi-ctrl
299              - qcom,sc7280-dsi-ctrl
300              - qcom,sm8150-dsi-ctrl
301              - qcom,sm8250-dsi-ctrl
302              - qcom,sm8350-dsi-ctrl
303              - qcom,sm8450-dsi-ctrl
304              - qcom,sm8550-dsi-ctrl
305    then:
306      properties:
307        clocks:
308          maxItems: 6
309        clock-names:
310          items:
311            - const: byte
312            - const: byte_intf
313            - const: pixel
314            - const: core
315            - const: iface
316            - const: bus
317
318  - if:
319      properties:
320        compatible:
321          contains:
322            enum:
323              - qcom,sdm660-dsi-ctrl
324    then:
325      properties:
326        clocks:
327          maxItems: 9
328        clock-names:
329          items:
330            - const: mdp_core
331            - const: byte
332            - const: byte_intf
333            - const: mnoc
334            - const: iface
335            - const: bus
336            - const: core_mmss
337            - const: pixel
338            - const: core
339
340  - if:
341      properties:
342        compatible:
343          contains:
344            enum:
345              - qcom,sdm845-dsi-ctrl
346    then:
347      properties:
348        clocks:
349          maxItems: 6
350        clock-names:
351          items:
352            - const: byte
353            - const: byte_intf
354            - const: pixel
355            - const: core
356            - const: iface
357            - const: bus
358
359unevaluatedProperties: false
360
361examples:
362  - |
363     #include <dt-bindings/interrupt-controller/arm-gic.h>
364     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
365     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
366     #include <dt-bindings/power/qcom-rpmpd.h>
367
368     dsi@ae94000 {
369           compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
370           reg = <0x0ae94000 0x400>;
371           reg-names = "dsi_ctrl";
372
373           #address-cells = <1>;
374           #size-cells = <0>;
375
376           interrupt-parent = <&mdss>;
377           interrupts = <4>;
378
379           clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
380                    <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
381                    <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
382                    <&dispcc DISP_CC_MDSS_ESC0_CLK>,
383                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
384                    <&dispcc DISP_CC_MDSS_AXI_CLK>;
385           clock-names = "byte",
386                         "byte_intf",
387                         "pixel",
388                         "core",
389                         "iface",
390                         "bus";
391
392           phys = <&dsi0_phy>;
393           phy-names = "dsi";
394
395           assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
396           assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
397
398           power-domains = <&rpmhpd SC7180_CX>;
399           operating-points-v2 = <&dsi_opp_table>;
400
401           ports {
402                  #address-cells = <1>;
403                  #size-cells = <0>;
404
405                  port@0 {
406                          reg = <0>;
407                          dsi0_in: endpoint {
408                                   remote-endpoint = <&dpu_intf1_out>;
409                          };
410                  };
411
412                  port@1 {
413                          reg = <1>;
414                          dsi0_out: endpoint {
415                                   remote-endpoint = <&sn65dsi86_in>;
416                                   data-lanes = <0 1 2 3>;
417                          };
418                  };
419           };
420     };
421...
422