1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DSI controller 8 9maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - qcom,apq8064-dsi-ctrl 18 - qcom,msm8916-dsi-ctrl 19 - qcom,msm8953-dsi-ctrl 20 - qcom,msm8974-dsi-ctrl 21 - qcom,msm8996-dsi-ctrl 22 - qcom,msm8998-dsi-ctrl 23 - qcom,qcm2290-dsi-ctrl 24 - qcom,sc7180-dsi-ctrl 25 - qcom,sc7280-dsi-ctrl 26 - qcom,sdm660-dsi-ctrl 27 - qcom,sdm845-dsi-ctrl 28 - qcom,sm6115-dsi-ctrl 29 - qcom,sm6350-dsi-ctrl 30 - qcom,sm6375-dsi-ctrl 31 - qcom,sm8150-dsi-ctrl 32 - qcom,sm8250-dsi-ctrl 33 - qcom,sm8350-dsi-ctrl 34 - qcom,sm8450-dsi-ctrl 35 - qcom,sm8550-dsi-ctrl 36 - const: qcom,mdss-dsi-ctrl 37 - enum: 38 - qcom,dsi-ctrl-6g-qcm2290 39 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible 40 deprecated: true 41 42 reg: 43 maxItems: 1 44 45 reg-names: 46 const: dsi_ctrl 47 48 interrupts: 49 maxItems: 1 50 51 clocks: 52 description: | 53 Several clocks are used, depending on the variant. Typical ones are:: 54 - bus:: Display AHB clock. 55 - byte:: Display byte clock. 56 - byte_intf:: Display byte interface clock. 57 - core:: Display core clock. 58 - core_mss:: Core MultiMedia SubSystem clock. 59 - iface:: Display AXI clock. 60 - mdp_core:: MDP Core clock. 61 - mnoc:: MNOC clock 62 - pixel:: Display pixel clock. 63 minItems: 3 64 maxItems: 9 65 66 clock-names: 67 minItems: 3 68 maxItems: 9 69 70 phys: 71 maxItems: 1 72 73 phy-names: 74 deprecated: true 75 const: dsi 76 77 syscon-sfpb: 78 description: A phandle to mmss_sfpb syscon node (only for DSIv2). 79 $ref: "/schemas/types.yaml#/definitions/phandle" 80 81 qcom,dual-dsi-mode: 82 type: boolean 83 description: | 84 Indicates if the DSI controller is driving a panel which needs 85 2 DSI links. 86 87 qcom,master-dsi: 88 type: boolean 89 description: | 90 Indicates if the DSI controller is the master DSI controller when 91 qcom,dual-dsi-mode enabled. 92 93 qcom,sync-dual-dsi: 94 type: boolean 95 description: | 96 Indicates if the DSI controller needs to sync the other DSI controller 97 with MIPI DCS commands when qcom,dual-dsi-mode enabled. 98 99 assigned-clocks: 100 minItems: 2 101 maxItems: 4 102 description: | 103 Parents of "byte" and "pixel" for the given platform. 104 For DSIv2 platforms this should contain "byte", "esc", "src" and 105 "pixel_src" clocks. 106 107 assigned-clock-parents: 108 minItems: 2 109 maxItems: 4 110 description: | 111 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. 112 113 power-domains: 114 maxItems: 1 115 116 operating-points-v2: true 117 118 opp-table: 119 type: object 120 121 ports: 122 $ref: "/schemas/graph.yaml#/properties/ports" 123 description: | 124 Contains DSI controller input and output ports as children, each 125 containing one endpoint subnode. 126 127 properties: 128 port@0: 129 $ref: "/schemas/graph.yaml#/$defs/port-base" 130 unevaluatedProperties: false 131 description: | 132 Input endpoints of the controller. 133 properties: 134 endpoint: 135 $ref: /schemas/media/video-interfaces.yaml# 136 unevaluatedProperties: false 137 properties: 138 data-lanes: 139 maxItems: 4 140 minItems: 1 141 items: 142 enum: [ 0, 1, 2, 3 ] 143 144 port@1: 145 $ref: "/schemas/graph.yaml#/$defs/port-base" 146 unevaluatedProperties: false 147 description: | 148 Output endpoints of the controller. 149 properties: 150 endpoint: 151 $ref: /schemas/media/video-interfaces.yaml# 152 unevaluatedProperties: false 153 properties: 154 data-lanes: 155 maxItems: 4 156 minItems: 1 157 items: 158 enum: [ 0, 1, 2, 3 ] 159 160 required: 161 - port@0 162 - port@1 163 164 avdd-supply: 165 description: 166 Phandle to vdd regulator device node 167 168 vcca-supply: 169 description: 170 Phandle to vdd regulator device node 171 172 vdd-supply: 173 description: 174 VDD regulator 175 176 vddio-supply: 177 description: 178 VDD-IO regulator 179 180 vdda-supply: 181 description: 182 VDDA regulator 183 184required: 185 - compatible 186 - reg 187 - reg-names 188 - interrupts 189 - clocks 190 - clock-names 191 - phys 192 - assigned-clocks 193 - assigned-clock-parents 194 - ports 195 196allOf: 197 - $ref: ../dsi-controller.yaml# 198 - if: 199 properties: 200 compatible: 201 contains: 202 enum: 203 - qcom,apq8064-dsi-ctrl 204 then: 205 properties: 206 clocks: 207 maxItems: 7 208 clock-names: 209 items: 210 - const: iface 211 - const: bus 212 - const: core_mmss 213 - const: src 214 - const: byte 215 - const: pixel 216 - const: core 217 218 - if: 219 properties: 220 compatible: 221 contains: 222 enum: 223 - qcom,msm8916-dsi-ctrl 224 then: 225 properties: 226 clocks: 227 maxItems: 6 228 clock-names: 229 items: 230 - const: mdp_core 231 - const: iface 232 - const: bus 233 - const: byte 234 - const: pixel 235 - const: core 236 237 - if: 238 properties: 239 compatible: 240 contains: 241 enum: 242 - qcom,msm8953-dsi-ctrl 243 then: 244 properties: 245 clocks: 246 maxItems: 6 247 clock-names: 248 items: 249 - const: mdp_core 250 - const: iface 251 - const: bus 252 - const: byte 253 - const: pixel 254 - const: core 255 256 - if: 257 properties: 258 compatible: 259 contains: 260 enum: 261 - qcom,msm8974-dsi-ctrl 262 then: 263 properties: 264 clocks: 265 maxItems: 7 266 clock-names: 267 items: 268 - const: mdp_core 269 - const: iface 270 - const: bus 271 - const: byte 272 - const: pixel 273 - const: core 274 - const: core_mmss 275 276 - if: 277 properties: 278 compatible: 279 contains: 280 enum: 281 - qcom,msm8996-dsi-ctrl 282 then: 283 properties: 284 clocks: 285 maxItems: 7 286 clock-names: 287 items: 288 - const: mdp_core 289 - const: byte 290 - const: iface 291 - const: bus 292 - const: core_mmss 293 - const: pixel 294 - const: core 295 296 - if: 297 properties: 298 compatible: 299 contains: 300 enum: 301 - qcom,msm8998-dsi-ctrl 302 - qcom,sm6350-dsi-ctrl 303 then: 304 properties: 305 clocks: 306 maxItems: 6 307 clock-names: 308 items: 309 - const: byte 310 - const: byte_intf 311 - const: pixel 312 - const: core 313 - const: iface 314 - const: bus 315 316 - if: 317 properties: 318 compatible: 319 contains: 320 enum: 321 - qcom,sc7180-dsi-ctrl 322 - qcom,sc7280-dsi-ctrl 323 - qcom,sm8150-dsi-ctrl 324 - qcom,sm8250-dsi-ctrl 325 - qcom,sm8350-dsi-ctrl 326 - qcom,sm8450-dsi-ctrl 327 - qcom,sm8550-dsi-ctrl 328 then: 329 properties: 330 clocks: 331 maxItems: 6 332 clock-names: 333 items: 334 - const: byte 335 - const: byte_intf 336 - const: pixel 337 - const: core 338 - const: iface 339 - const: bus 340 341 - if: 342 properties: 343 compatible: 344 contains: 345 enum: 346 - qcom,sdm660-dsi-ctrl 347 then: 348 properties: 349 clocks: 350 maxItems: 9 351 clock-names: 352 items: 353 - const: mdp_core 354 - const: byte 355 - const: byte_intf 356 - const: mnoc 357 - const: iface 358 - const: bus 359 - const: core_mmss 360 - const: pixel 361 - const: core 362 363 - if: 364 properties: 365 compatible: 366 contains: 367 enum: 368 - qcom,sdm845-dsi-ctrl 369 - qcom,sm6115-dsi-ctrl 370 - qcom,sm6375-dsi-ctrl 371 then: 372 properties: 373 clocks: 374 maxItems: 6 375 clock-names: 376 items: 377 - const: byte 378 - const: byte_intf 379 - const: pixel 380 - const: core 381 - const: iface 382 - const: bus 383 384unevaluatedProperties: false 385 386examples: 387 - | 388 #include <dt-bindings/interrupt-controller/arm-gic.h> 389 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 390 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 391 #include <dt-bindings/power/qcom-rpmpd.h> 392 393 dsi@ae94000 { 394 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 395 reg = <0x0ae94000 0x400>; 396 reg-names = "dsi_ctrl"; 397 398 #address-cells = <1>; 399 #size-cells = <0>; 400 401 interrupt-parent = <&mdss>; 402 interrupts = <4>; 403 404 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 405 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 406 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 407 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 408 <&dispcc DISP_CC_MDSS_AHB_CLK>, 409 <&dispcc DISP_CC_MDSS_AXI_CLK>; 410 clock-names = "byte", 411 "byte_intf", 412 "pixel", 413 "core", 414 "iface", 415 "bus"; 416 417 phys = <&dsi0_phy>; 418 phy-names = "dsi"; 419 420 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 421 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 422 423 power-domains = <&rpmhpd SC7180_CX>; 424 operating-points-v2 = <&dsi_opp_table>; 425 426 ports { 427 #address-cells = <1>; 428 #size-cells = <0>; 429 430 port@0 { 431 reg = <0>; 432 dsi0_in: endpoint { 433 remote-endpoint = <&dpu_intf1_out>; 434 }; 435 }; 436 437 port@1 { 438 reg = <1>; 439 dsi0_out: endpoint { 440 remote-endpoint = <&sn65dsi86_in>; 441 data-lanes = <0 1 2 3>; 442 }; 443 }; 444 }; 445 }; 446... 447