1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DSI controller 8 9maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - qcom,apq8064-dsi-ctrl 18 - qcom,msm8226-dsi-ctrl 19 - qcom,msm8916-dsi-ctrl 20 - qcom,msm8953-dsi-ctrl 21 - qcom,msm8974-dsi-ctrl 22 - qcom,msm8996-dsi-ctrl 23 - qcom,msm8998-dsi-ctrl 24 - qcom,qcm2290-dsi-ctrl 25 - qcom,sc7180-dsi-ctrl 26 - qcom,sc7280-dsi-ctrl 27 - qcom,sdm660-dsi-ctrl 28 - qcom,sdm845-dsi-ctrl 29 - qcom,sm6115-dsi-ctrl 30 - qcom,sm6350-dsi-ctrl 31 - qcom,sm6375-dsi-ctrl 32 - qcom,sm8150-dsi-ctrl 33 - qcom,sm8250-dsi-ctrl 34 - qcom,sm8350-dsi-ctrl 35 - qcom,sm8450-dsi-ctrl 36 - qcom,sm8550-dsi-ctrl 37 - const: qcom,mdss-dsi-ctrl 38 - enum: 39 - qcom,dsi-ctrl-6g-qcm2290 40 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible 41 deprecated: true 42 43 reg: 44 maxItems: 1 45 46 reg-names: 47 const: dsi_ctrl 48 49 interrupts: 50 maxItems: 1 51 52 clocks: 53 description: | 54 Several clocks are used, depending on the variant. Typical ones are:: 55 - bus:: Display AHB clock. 56 - byte:: Display byte clock. 57 - byte_intf:: Display byte interface clock. 58 - core:: Display core clock. 59 - core_mss:: Core MultiMedia SubSystem clock. 60 - iface:: Display AXI clock. 61 - mdp_core:: MDP Core clock. 62 - mnoc:: MNOC clock 63 - pixel:: Display pixel clock. 64 minItems: 3 65 maxItems: 9 66 67 clock-names: 68 minItems: 3 69 maxItems: 9 70 71 phys: 72 maxItems: 1 73 74 phy-names: 75 deprecated: true 76 const: dsi 77 78 syscon-sfpb: 79 description: A phandle to mmss_sfpb syscon node (only for DSIv2). 80 $ref: /schemas/types.yaml#/definitions/phandle 81 82 qcom,dual-dsi-mode: 83 type: boolean 84 description: | 85 Indicates if the DSI controller is driving a panel which needs 86 2 DSI links. 87 88 qcom,master-dsi: 89 type: boolean 90 description: | 91 Indicates if the DSI controller is the master DSI controller when 92 qcom,dual-dsi-mode enabled. 93 94 qcom,sync-dual-dsi: 95 type: boolean 96 description: | 97 Indicates if the DSI controller needs to sync the other DSI controller 98 with MIPI DCS commands when qcom,dual-dsi-mode enabled. 99 100 assigned-clocks: 101 minItems: 2 102 maxItems: 4 103 description: | 104 Parents of "byte" and "pixel" for the given platform. 105 For DSIv2 platforms this should contain "byte", "esc", "src" and 106 "pixel_src" clocks. 107 108 assigned-clock-parents: 109 minItems: 2 110 maxItems: 4 111 description: | 112 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. 113 114 power-domains: 115 maxItems: 1 116 117 operating-points-v2: true 118 119 opp-table: 120 type: object 121 122 ports: 123 $ref: /schemas/graph.yaml#/properties/ports 124 description: | 125 Contains DSI controller input and output ports as children, each 126 containing one endpoint subnode. 127 128 properties: 129 port@0: 130 $ref: /schemas/graph.yaml#/$defs/port-base 131 unevaluatedProperties: false 132 description: | 133 Input endpoints of the controller. 134 properties: 135 endpoint: 136 $ref: /schemas/media/video-interfaces.yaml# 137 unevaluatedProperties: false 138 properties: 139 data-lanes: 140 maxItems: 4 141 minItems: 1 142 items: 143 enum: [ 0, 1, 2, 3 ] 144 145 port@1: 146 $ref: /schemas/graph.yaml#/$defs/port-base 147 unevaluatedProperties: false 148 description: | 149 Output endpoints of the controller. 150 properties: 151 endpoint: 152 $ref: /schemas/media/video-interfaces.yaml# 153 unevaluatedProperties: false 154 properties: 155 data-lanes: 156 maxItems: 4 157 minItems: 1 158 items: 159 enum: [ 0, 1, 2, 3 ] 160 161 required: 162 - port@0 163 - port@1 164 165 avdd-supply: 166 description: 167 Phandle to vdd regulator device node 168 169 refgen-supply: 170 description: 171 Phandle to REFGEN regulator device node 172 173 vcca-supply: 174 description: 175 Phandle to vdd regulator device node 176 177 vdd-supply: 178 description: 179 VDD regulator 180 181 vddio-supply: 182 description: 183 VDD-IO regulator 184 185 vdda-supply: 186 description: 187 VDDA regulator 188 189required: 190 - compatible 191 - reg 192 - reg-names 193 - interrupts 194 - clocks 195 - clock-names 196 - phys 197 - assigned-clocks 198 - assigned-clock-parents 199 - ports 200 201allOf: 202 - $ref: ../dsi-controller.yaml# 203 - if: 204 properties: 205 compatible: 206 contains: 207 enum: 208 - qcom,apq8064-dsi-ctrl 209 then: 210 properties: 211 clocks: 212 maxItems: 7 213 clock-names: 214 items: 215 - const: iface 216 - const: bus 217 - const: core_mmss 218 - const: src 219 - const: byte 220 - const: pixel 221 - const: core 222 223 - if: 224 properties: 225 compatible: 226 contains: 227 enum: 228 - qcom,msm8916-dsi-ctrl 229 then: 230 properties: 231 clocks: 232 maxItems: 6 233 clock-names: 234 items: 235 - const: mdp_core 236 - const: iface 237 - const: bus 238 - const: byte 239 - const: pixel 240 - const: core 241 242 - if: 243 properties: 244 compatible: 245 contains: 246 enum: 247 - qcom,msm8953-dsi-ctrl 248 then: 249 properties: 250 clocks: 251 maxItems: 6 252 clock-names: 253 items: 254 - const: mdp_core 255 - const: iface 256 - const: bus 257 - const: byte 258 - const: pixel 259 - const: core 260 261 - if: 262 properties: 263 compatible: 264 contains: 265 enum: 266 - qcom,msm8226-dsi-ctrl 267 - qcom,msm8974-dsi-ctrl 268 then: 269 properties: 270 clocks: 271 maxItems: 7 272 clock-names: 273 items: 274 - const: mdp_core 275 - const: iface 276 - const: bus 277 - const: byte 278 - const: pixel 279 - const: core 280 - const: core_mmss 281 282 - if: 283 properties: 284 compatible: 285 contains: 286 enum: 287 - qcom,msm8996-dsi-ctrl 288 then: 289 properties: 290 clocks: 291 maxItems: 7 292 clock-names: 293 items: 294 - const: mdp_core 295 - const: byte 296 - const: iface 297 - const: bus 298 - const: core_mmss 299 - const: pixel 300 - const: core 301 302 - if: 303 properties: 304 compatible: 305 contains: 306 enum: 307 - qcom,msm8998-dsi-ctrl 308 - qcom,sm6350-dsi-ctrl 309 then: 310 properties: 311 clocks: 312 maxItems: 6 313 clock-names: 314 items: 315 - const: byte 316 - const: byte_intf 317 - const: pixel 318 - const: core 319 - const: iface 320 - const: bus 321 322 - if: 323 properties: 324 compatible: 325 contains: 326 enum: 327 - qcom,sc7180-dsi-ctrl 328 - qcom,sc7280-dsi-ctrl 329 - qcom,sm8150-dsi-ctrl 330 - qcom,sm8250-dsi-ctrl 331 - qcom,sm8350-dsi-ctrl 332 - qcom,sm8450-dsi-ctrl 333 - qcom,sm8550-dsi-ctrl 334 then: 335 properties: 336 clocks: 337 maxItems: 6 338 clock-names: 339 items: 340 - const: byte 341 - const: byte_intf 342 - const: pixel 343 - const: core 344 - const: iface 345 - const: bus 346 347 - if: 348 properties: 349 compatible: 350 contains: 351 enum: 352 - qcom,sdm660-dsi-ctrl 353 then: 354 properties: 355 clocks: 356 maxItems: 9 357 clock-names: 358 items: 359 - const: mdp_core 360 - const: byte 361 - const: byte_intf 362 - const: mnoc 363 - const: iface 364 - const: bus 365 - const: core_mmss 366 - const: pixel 367 - const: core 368 369 - if: 370 properties: 371 compatible: 372 contains: 373 enum: 374 - qcom,sdm845-dsi-ctrl 375 - qcom,sm6115-dsi-ctrl 376 - qcom,sm6375-dsi-ctrl 377 then: 378 properties: 379 clocks: 380 maxItems: 6 381 clock-names: 382 items: 383 - const: byte 384 - const: byte_intf 385 - const: pixel 386 - const: core 387 - const: iface 388 - const: bus 389 390unevaluatedProperties: false 391 392examples: 393 - | 394 #include <dt-bindings/interrupt-controller/arm-gic.h> 395 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 396 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 397 #include <dt-bindings/power/qcom-rpmpd.h> 398 399 dsi@ae94000 { 400 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 401 reg = <0x0ae94000 0x400>; 402 reg-names = "dsi_ctrl"; 403 404 #address-cells = <1>; 405 #size-cells = <0>; 406 407 interrupt-parent = <&mdss>; 408 interrupts = <4>; 409 410 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 411 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 412 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 413 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 414 <&dispcc DISP_CC_MDSS_AHB_CLK>, 415 <&dispcc DISP_CC_MDSS_AXI_CLK>; 416 clock-names = "byte", 417 "byte_intf", 418 "pixel", 419 "core", 420 "iface", 421 "bus"; 422 423 phys = <&dsi0_phy>; 424 phy-names = "dsi"; 425 426 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 427 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 428 429 power-domains = <&rpmhpd SC7180_CX>; 430 operating-points-v2 = <&dsi_opp_table>; 431 432 ports { 433 #address-cells = <1>; 434 #size-cells = <0>; 435 436 port@0 { 437 reg = <0>; 438 dsi0_in: endpoint { 439 remote-endpoint = <&dpu_intf1_out>; 440 }; 441 }; 442 443 port@1 { 444 reg = <1>; 445 dsi0_out: endpoint { 446 remote-endpoint = <&sn65dsi86_in>; 447 data-lanes = <0 1 2 3>; 448 }; 449 }; 450 }; 451 }; 452... 453