1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DSI controller 8 9maintainers: 10 - Krishna Manikandan <quic_mkrishn@quicinc.com> 11 12allOf: 13 - $ref: "../dsi-controller.yaml#" 14 15properties: 16 compatible: 17 oneOf: 18 - items: 19 - enum: 20 - qcom,apq8064-dsi-ctrl 21 - qcom,msm8916-dsi-ctrl 22 - qcom,msm8953-dsi-ctrl 23 - qcom,msm8974-dsi-ctrl 24 - qcom,msm8996-dsi-ctrl 25 - qcom,msm8998-dsi-ctrl 26 - qcom,qcm2290-dsi-ctrl 27 - qcom,sc7180-dsi-ctrl 28 - qcom,sc7280-dsi-ctrl 29 - qcom,sdm660-dsi-ctrl 30 - qcom,sdm845-dsi-ctrl 31 - qcom,sm8150-dsi-ctrl 32 - qcom,sm8250-dsi-ctrl 33 - qcom,sm8350-dsi-ctrl 34 - qcom,sm8450-dsi-ctrl 35 - qcom,sm8550-dsi-ctrl 36 - const: qcom,mdss-dsi-ctrl 37 - items: 38 - enum: 39 - dsi-ctrl-6g-qcm2290 40 - const: qcom,mdss-dsi-ctrl 41 deprecated: true 42 43 reg: 44 maxItems: 1 45 46 reg-names: 47 const: dsi_ctrl 48 49 interrupts: 50 maxItems: 1 51 52 clocks: 53 items: 54 - description: Display byte clock 55 - description: Display byte interface clock 56 - description: Display pixel clock 57 - description: Display core clock 58 - description: Display AHB clock 59 - description: Display AXI clock 60 61 clock-names: 62 items: 63 - const: byte 64 - const: byte_intf 65 - const: pixel 66 - const: core 67 - const: iface 68 - const: bus 69 70 phys: 71 maxItems: 1 72 73 phy-names: 74 deprecated: true 75 const: dsi 76 77 "#address-cells": true 78 79 "#size-cells": true 80 81 syscon-sfpb: 82 description: A phandle to mmss_sfpb syscon node (only for DSIv2). 83 $ref: "/schemas/types.yaml#/definitions/phandle" 84 85 qcom,dual-dsi-mode: 86 type: boolean 87 description: | 88 Indicates if the DSI controller is driving a panel which needs 89 2 DSI links. 90 91 assigned-clocks: 92 maxItems: 2 93 description: | 94 Parents of "byte" and "pixel" for the given platform. 95 96 assigned-clock-parents: 97 maxItems: 2 98 description: | 99 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. 100 101 power-domains: 102 maxItems: 1 103 104 operating-points-v2: true 105 106 opp-table: 107 type: object 108 109 ports: 110 $ref: "/schemas/graph.yaml#/properties/ports" 111 description: | 112 Contains DSI controller input and output ports as children, each 113 containing one endpoint subnode. 114 115 properties: 116 port@0: 117 $ref: "/schemas/graph.yaml#/$defs/port-base" 118 unevaluatedProperties: false 119 description: | 120 Input endpoints of the controller. 121 properties: 122 endpoint: 123 $ref: /schemas/media/video-interfaces.yaml# 124 unevaluatedProperties: false 125 properties: 126 data-lanes: 127 maxItems: 4 128 minItems: 4 129 items: 130 enum: [ 0, 1, 2, 3 ] 131 132 port@1: 133 $ref: "/schemas/graph.yaml#/$defs/port-base" 134 unevaluatedProperties: false 135 description: | 136 Output endpoints of the controller. 137 properties: 138 endpoint: 139 $ref: /schemas/media/video-interfaces.yaml# 140 unevaluatedProperties: false 141 properties: 142 data-lanes: 143 maxItems: 4 144 minItems: 4 145 items: 146 enum: [ 0, 1, 2, 3 ] 147 148 required: 149 - port@0 150 - port@1 151 152 vdd-supply: 153 description: 154 VDD regulator 155 156 vddio-supply: 157 description: 158 VDD-IO regulator 159 160 vdda-supply: 161 description: 162 VDDA regulator 163 164required: 165 - compatible 166 - reg 167 - reg-names 168 - interrupts 169 - clocks 170 - clock-names 171 - phys 172 - assigned-clocks 173 - assigned-clock-parents 174 - ports 175 176additionalProperties: false 177 178examples: 179 - | 180 #include <dt-bindings/interrupt-controller/arm-gic.h> 181 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 182 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 183 #include <dt-bindings/power/qcom-rpmpd.h> 184 185 dsi@ae94000 { 186 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 187 reg = <0x0ae94000 0x400>; 188 reg-names = "dsi_ctrl"; 189 190 #address-cells = <1>; 191 #size-cells = <0>; 192 193 interrupt-parent = <&mdss>; 194 interrupts = <4>; 195 196 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 197 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 198 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 199 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 200 <&dispcc DISP_CC_MDSS_AHB_CLK>, 201 <&dispcc DISP_CC_MDSS_AXI_CLK>; 202 clock-names = "byte", 203 "byte_intf", 204 "pixel", 205 "core", 206 "iface", 207 "bus"; 208 209 phys = <&dsi0_phy>; 210 phy-names = "dsi"; 211 212 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 213 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 214 215 power-domains = <&rpmhpd SC7180_CX>; 216 operating-points-v2 = <&dsi_opp_table>; 217 218 ports { 219 #address-cells = <1>; 220 #size-cells = <0>; 221 222 port@0 { 223 reg = <0>; 224 dsi0_in: endpoint { 225 remote-endpoint = <&dpu_intf1_out>; 226 }; 227 }; 228 229 port@1 { 230 reg = <1>; 231 dsi0_out: endpoint { 232 remote-endpoint = <&sn65dsi86_in>; 233 data-lanes = <0 1 2 3>; 234 }; 235 }; 236 }; 237 }; 238... 239