1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Display DSI controller 8 9maintainers: 10 - Krishna Manikandan <mkrishn@codeaurora.org> 11 12allOf: 13 - $ref: "../dsi-controller.yaml#" 14 15properties: 16 compatible: 17 items: 18 - const: qcom,mdss-dsi-ctrl 19 20 reg: 21 maxItems: 1 22 23 reg-names: 24 const: dsi_ctrl 25 26 interrupts: 27 maxItems: 1 28 29 clocks: 30 items: 31 - description: Display byte clock 32 - description: Display byte interface clock 33 - description: Display pixel clock 34 - description: Display escape clock 35 - description: Display AHB clock 36 - description: Display AXI clock 37 38 clock-names: 39 items: 40 - const: byte 41 - const: byte_intf 42 - const: pixel 43 - const: core 44 - const: iface 45 - const: bus 46 47 phys: 48 maxItems: 1 49 50 phy-names: 51 const: dsi 52 53 "#address-cells": true 54 55 "#size-cells": true 56 57 syscon-sfpb: 58 description: A phandle to mmss_sfpb syscon node (only for DSIv2). 59 $ref: "/schemas/types.yaml#/definitions/phandle" 60 61 qcom,dual-dsi-mode: 62 type: boolean 63 description: | 64 Indicates if the DSI controller is driving a panel which needs 65 2 DSI links. 66 67 assigned-clocks: 68 minItems: 2 69 maxItems: 2 70 description: | 71 Parents of "byte" and "pixel" for the given platform. 72 73 assigned-clock-parents: 74 minItems: 2 75 maxItems: 2 76 description: | 77 The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. 78 79 power-domains: 80 maxItems: 1 81 82 operating-points-v2: true 83 84 ports: 85 $ref: "/schemas/graph.yaml#/properties/ports" 86 description: | 87 Contains DSI controller input and output ports as children, each 88 containing one endpoint subnode. 89 90 properties: 91 port@0: 92 $ref: "/schemas/graph.yaml#/properties/port" 93 description: | 94 Input endpoints of the controller. 95 properties: 96 endpoint: 97 $ref: /schemas/media/video-interfaces.yaml# 98 unevaluatedProperties: false 99 properties: 100 data-lanes: 101 maxItems: 4 102 minItems: 4 103 items: 104 enum: [ 0, 1, 2, 3 ] 105 106 port@1: 107 $ref: "/schemas/graph.yaml#/properties/port" 108 description: | 109 Output endpoints of the controller. 110 properties: 111 endpoint: 112 $ref: /schemas/media/video-interfaces.yaml# 113 unevaluatedProperties: false 114 properties: 115 data-lanes: 116 maxItems: 4 117 minItems: 4 118 items: 119 enum: [ 0, 1, 2, 3 ] 120 121 required: 122 - port@0 123 - port@1 124 125required: 126 - compatible 127 - reg 128 - reg-names 129 - interrupts 130 - clocks 131 - clock-names 132 - phys 133 - phy-names 134 - assigned-clocks 135 - assigned-clock-parents 136 - power-domains 137 - operating-points-v2 138 - ports 139 140additionalProperties: false 141 142examples: 143 - | 144 #include <dt-bindings/interrupt-controller/arm-gic.h> 145 #include <dt-bindings/clock/qcom,dispcc-sdm845.h> 146 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 147 #include <dt-bindings/power/qcom-rpmpd.h> 148 149 dsi@ae94000 { 150 compatible = "qcom,mdss-dsi-ctrl"; 151 reg = <0x0ae94000 0x400>; 152 reg-names = "dsi_ctrl"; 153 154 #address-cells = <1>; 155 #size-cells = <0>; 156 157 interrupt-parent = <&mdss>; 158 interrupts = <4>; 159 160 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 161 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 162 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 163 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 164 <&dispcc DISP_CC_MDSS_AHB_CLK>, 165 <&dispcc DISP_CC_MDSS_AXI_CLK>; 166 clock-names = "byte", 167 "byte_intf", 168 "pixel", 169 "core", 170 "iface", 171 "bus"; 172 173 phys = <&dsi0_phy>; 174 phy-names = "dsi"; 175 176 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 177 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>; 178 179 power-domains = <&rpmhpd SC7180_CX>; 180 operating-points-v2 = <&dsi_opp_table>; 181 182 ports { 183 #address-cells = <1>; 184 #size-cells = <0>; 185 186 port@0 { 187 reg = <0>; 188 dsi0_in: endpoint { 189 remote-endpoint = <&dpu_intf1_out>; 190 }; 191 }; 192 193 port@1 { 194 reg = <1>; 195 dsi0_out: endpoint { 196 remote-endpoint = <&sn65dsi86_in>; 197 data-lanes = <0 1 2 3>; 198 }; 199 }; 200 }; 201 }; 202... 203