1# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI controller
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12properties:
13  compatible:
14    oneOf:
15      - items:
16          - enum:
17              - qcom,apq8064-dsi-ctrl
18              - qcom,msm8916-dsi-ctrl
19              - qcom,msm8953-dsi-ctrl
20              - qcom,msm8974-dsi-ctrl
21              - qcom,msm8996-dsi-ctrl
22              - qcom,msm8998-dsi-ctrl
23              - qcom,qcm2290-dsi-ctrl
24              - qcom,sc7180-dsi-ctrl
25              - qcom,sc7280-dsi-ctrl
26              - qcom,sdm660-dsi-ctrl
27              - qcom,sdm845-dsi-ctrl
28              - qcom,sm8150-dsi-ctrl
29              - qcom,sm8250-dsi-ctrl
30              - qcom,sm8350-dsi-ctrl
31              - qcom,sm8450-dsi-ctrl
32              - qcom,sm8550-dsi-ctrl
33          - const: qcom,mdss-dsi-ctrl
34      - items:
35          - enum:
36              - dsi-ctrl-6g-qcm2290
37          - const: qcom,mdss-dsi-ctrl
38        deprecated: true
39
40  reg:
41    maxItems: 1
42
43  reg-names:
44    const: dsi_ctrl
45
46  interrupts:
47    maxItems: 1
48
49  clocks:
50    description: |
51      Several clocks are used, depending on the variant. Typical ones are::
52       - bus:: Display AHB clock.
53       - byte:: Display byte clock.
54       - byte_intf:: Display byte interface clock.
55       - core:: Display core clock.
56       - core_mss:: Core MultiMedia SubSystem clock.
57       - iface:: Display AXI clock.
58       - mdp_core:: MDP Core clock.
59       - mnoc:: MNOC clock
60       - pixel:: Display pixel clock.
61    minItems: 3
62    maxItems: 9
63
64  clock-names:
65    minItems: 3
66    maxItems: 9
67
68  phys:
69    maxItems: 1
70
71  phy-names:
72    deprecated: true
73    const: dsi
74
75  syscon-sfpb:
76    description: A phandle to mmss_sfpb syscon node (only for DSIv2).
77    $ref: "/schemas/types.yaml#/definitions/phandle"
78
79  qcom,dual-dsi-mode:
80    type: boolean
81    description: |
82      Indicates if the DSI controller is driving a panel which needs
83      2 DSI links.
84
85  assigned-clocks:
86    minItems: 2
87    maxItems: 4
88    description: |
89      Parents of "byte" and "pixel" for the given platform.
90      For DSIv2 platforms this should contain "byte", "esc", "src" and
91      "pixel_src" clocks.
92
93  assigned-clock-parents:
94    minItems: 2
95    maxItems: 4
96    description: |
97      The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
98
99  power-domains:
100    maxItems: 1
101
102  operating-points-v2: true
103
104  opp-table:
105    type: object
106
107  ports:
108    $ref: "/schemas/graph.yaml#/properties/ports"
109    description: |
110      Contains DSI controller input and output ports as children, each
111      containing one endpoint subnode.
112
113    properties:
114      port@0:
115        $ref: "/schemas/graph.yaml#/$defs/port-base"
116        unevaluatedProperties: false
117        description: |
118          Input endpoints of the controller.
119        properties:
120          endpoint:
121            $ref: /schemas/media/video-interfaces.yaml#
122            unevaluatedProperties: false
123            properties:
124              data-lanes:
125                maxItems: 4
126                minItems: 1
127                items:
128                  enum: [ 0, 1, 2, 3 ]
129
130      port@1:
131        $ref: "/schemas/graph.yaml#/$defs/port-base"
132        unevaluatedProperties: false
133        description: |
134          Output endpoints of the controller.
135        properties:
136          endpoint:
137            $ref: /schemas/media/video-interfaces.yaml#
138            unevaluatedProperties: false
139            properties:
140              data-lanes:
141                maxItems: 4
142                minItems: 1
143                items:
144                  enum: [ 0, 1, 2, 3 ]
145
146    required:
147      - port@0
148      - port@1
149
150  avdd-supply:
151    description:
152      Phandle to vdd regulator device node
153
154  vcca-supply:
155    description:
156      Phandle to vdd regulator device node
157
158  vdd-supply:
159    description:
160      VDD regulator
161
162  vddio-supply:
163    description:
164      VDD-IO regulator
165
166  vdda-supply:
167    description:
168      VDDA regulator
169
170required:
171  - compatible
172  - reg
173  - reg-names
174  - interrupts
175  - clocks
176  - clock-names
177  - phys
178  - assigned-clocks
179  - assigned-clock-parents
180  - ports
181
182allOf:
183  - $ref: ../dsi-controller.yaml#
184  - if:
185      properties:
186        compatible:
187          contains:
188            enum:
189              - qcom,apq8064-dsi-ctrl
190    then:
191      properties:
192        clocks:
193          maxItems: 7
194        clock-names:
195          items:
196            - const: iface
197            - const: bus
198            - const: core_mmss
199            - const: src
200            - const: byte
201            - const: pixel
202            - const: core
203
204  - if:
205      properties:
206        compatible:
207          contains:
208            enum:
209              - qcom,msm8916-dsi-ctrl
210    then:
211      properties:
212        clocks:
213          maxItems: 6
214        clock-names:
215          items:
216            - const: mdp_core
217            - const: iface
218            - const: bus
219            - const: byte
220            - const: pixel
221            - const: core
222
223  - if:
224      properties:
225        compatible:
226          contains:
227            enum:
228              - qcom,msm8953-dsi-ctrl
229    then:
230      properties:
231        clocks:
232          maxItems: 6
233        clock-names:
234          items:
235            - const: mdp_core
236            - const: iface
237            - const: bus
238            - const: byte
239            - const: pixel
240            - const: core
241
242  - if:
243      properties:
244        compatible:
245          contains:
246            enum:
247              - qcom,msm8974-dsi-ctrl
248    then:
249      properties:
250        clocks:
251          maxItems: 7
252        clock-names:
253          items:
254            - const: mdp_core
255            - const: iface
256            - const: bus
257            - const: byte
258            - const: pixel
259            - const: core
260            - const: core_mmss
261
262  - if:
263      properties:
264        compatible:
265          contains:
266            enum:
267              - qcom,msm8996-dsi-ctrl
268    then:
269      properties:
270        clocks:
271          maxItems: 7
272        clock-names:
273          items:
274            - const: mdp_core
275            - const: byte
276            - const: iface
277            - const: bus
278            - const: core_mmss
279            - const: pixel
280            - const: core
281
282  - if:
283      properties:
284        compatible:
285          contains:
286            enum:
287              - qcom,msm8998-dsi-ctrl
288    then:
289      properties:
290        clocks:
291          maxItems: 6
292        clock-names:
293          items:
294            - const: byte
295            - const: byte_intf
296            - const: pixel
297            - const: core
298            - const: iface
299            - const: bus
300
301  - if:
302      properties:
303        compatible:
304          contains:
305            enum:
306              - qcom,sc7180-dsi-ctrl
307              - qcom,sc7280-dsi-ctrl
308              - qcom,sm8150-dsi-ctrl
309              - qcom,sm8250-dsi-ctrl
310              - qcom,sm8350-dsi-ctrl
311              - qcom,sm8450-dsi-ctrl
312              - qcom,sm8550-dsi-ctrl
313    then:
314      properties:
315        clocks:
316          maxItems: 6
317        clock-names:
318          items:
319            - const: byte
320            - const: byte_intf
321            - const: pixel
322            - const: core
323            - const: iface
324            - const: bus
325
326  - if:
327      properties:
328        compatible:
329          contains:
330            enum:
331              - qcom,sdm660-dsi-ctrl
332    then:
333      properties:
334        clocks:
335          maxItems: 9
336        clock-names:
337          items:
338            - const: mdp_core
339            - const: byte
340            - const: byte_intf
341            - const: mnoc
342            - const: iface
343            - const: bus
344            - const: core_mmss
345            - const: pixel
346            - const: core
347
348  - if:
349      properties:
350        compatible:
351          contains:
352            enum:
353              - qcom,sdm845-dsi-ctrl
354    then:
355      properties:
356        clocks:
357          maxItems: 6
358        clock-names:
359          items:
360            - const: byte
361            - const: byte_intf
362            - const: pixel
363            - const: core
364            - const: iface
365            - const: bus
366
367unevaluatedProperties: false
368
369examples:
370  - |
371     #include <dt-bindings/interrupt-controller/arm-gic.h>
372     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
373     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
374     #include <dt-bindings/power/qcom-rpmpd.h>
375
376     dsi@ae94000 {
377           compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
378           reg = <0x0ae94000 0x400>;
379           reg-names = "dsi_ctrl";
380
381           #address-cells = <1>;
382           #size-cells = <0>;
383
384           interrupt-parent = <&mdss>;
385           interrupts = <4>;
386
387           clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
388                    <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
389                    <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
390                    <&dispcc DISP_CC_MDSS_ESC0_CLK>,
391                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
392                    <&dispcc DISP_CC_MDSS_AXI_CLK>;
393           clock-names = "byte",
394                         "byte_intf",
395                         "pixel",
396                         "core",
397                         "iface",
398                         "bus";
399
400           phys = <&dsi0_phy>;
401           phy-names = "dsi";
402
403           assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
404           assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
405
406           power-domains = <&rpmhpd SC7180_CX>;
407           operating-points-v2 = <&dsi_opp_table>;
408
409           ports {
410                  #address-cells = <1>;
411                  #size-cells = <0>;
412
413                  port@0 {
414                          reg = <0>;
415                          dsi0_in: endpoint {
416                                   remote-endpoint = <&dpu_intf1_out>;
417                          };
418                  };
419
420                  port@1 {
421                          reg = <1>;
422                          dsi0_out: endpoint {
423                                   remote-endpoint = <&sn65dsi86_in>;
424                                   data-lanes = <0 1 2 3>;
425                          };
426                  };
427           };
428     };
429...
430