1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MSM Display Port Controller
8
9maintainers:
10  - Kuogee Hsieh <quic_khsieh@quicinc.com>
11
12description: |
13  Device tree bindings for DisplayPort host controller for MSM targets
14  that are compatible with VESA DisplayPort interface specification.
15
16properties:
17  compatible:
18    oneOf:
19      - enum:
20          - qcom,sc7180-dp
21          - qcom,sc7280-dp
22          - qcom,sc7280-edp
23          - qcom,sc8180x-dp
24          - qcom,sc8180x-edp
25          - qcom,sc8280xp-dp
26          - qcom,sc8280xp-edp
27          - qcom,sdm845-dp
28          - qcom,sm8350-dp
29      - items:
30          - enum:
31              - qcom,sm8450-dp
32          - const: qcom,sm8350-dp
33
34  reg:
35    minItems: 4
36    items:
37      - description: ahb register block
38      - description: aux register block
39      - description: link register block
40      - description: p0 register block
41      - description: p1 register block
42
43  interrupts:
44    maxItems: 1
45
46  clocks:
47    items:
48      - description: AHB clock to enable register access
49      - description: Display Port AUX clock
50      - description: Display Port Link clock
51      - description: Link interface clock between DP and PHY
52      - description: Display Port Pixel clock
53
54  clock-names:
55    items:
56      - const: core_iface
57      - const: core_aux
58      - const: ctrl_link
59      - const: ctrl_link_iface
60      - const: stream_pixel
61
62  assigned-clocks:
63    items:
64      - description: link clock source
65      - description: pixel clock source
66
67  assigned-clock-parents:
68    items:
69      - description: phy 0 parent
70      - description: phy 1 parent
71
72  phys:
73    maxItems: 1
74
75  phy-names:
76    items:
77      - const: dp
78
79  operating-points-v2: true
80
81  opp-table: true
82
83  power-domains:
84    maxItems: 1
85
86  aux-bus:
87    $ref: /schemas/display/dp-aux-bus.yaml#
88
89  data-lanes:
90    $ref: /schemas/types.yaml#/definitions/uint32-array
91    deprecated: true
92    minItems: 1
93    maxItems: 4
94    items:
95      maximum: 3
96
97  "#sound-dai-cells":
98    const: 0
99
100  vdda-0p9-supply:
101    deprecated: true
102  vdda-1p2-supply:
103    deprecated: true
104
105  ports:
106    $ref: /schemas/graph.yaml#/properties/ports
107    properties:
108      port@0:
109        $ref: /schemas/graph.yaml#/properties/port
110        description: Input endpoint of the controller
111
112      port@1:
113        $ref: /schemas/graph.yaml#/$defs/port-base
114        description: Output endpoint of the controller
115        properties:
116          endpoint:
117            $ref: /schemas/media/video-interfaces.yaml#
118            unevaluatedProperties: false
119            properties:
120              data-lanes:
121                minItems: 1
122                maxItems: 4
123                items:
124                  enum: [ 0, 1, 2, 3 ]
125
126              link-frequencies:
127                minItems: 1
128                maxItems: 4
129                items:
130                  enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
131
132    required:
133      - port@0
134      - port@1
135
136required:
137  - compatible
138  - reg
139  - interrupts
140  - clocks
141  - clock-names
142  - phys
143  - phy-names
144  - power-domains
145  - ports
146
147allOf:
148  # AUX BUS does not exist on DP controllers
149  # Audio output also is present only on DP output
150  # p1 regions is present on DP, but not on eDP
151  - if:
152      properties:
153        compatible:
154          contains:
155            enum:
156              - qcom,sc7280-edp
157              - qcom,sc8180x-edp
158              - qcom,sc8280xp-edp
159    then:
160      properties:
161        "#sound-dai-cells": false
162    else:
163      properties:
164        aux-bus: false
165        reg:
166          minItems: 5
167      required:
168        - "#sound-dai-cells"
169
170additionalProperties: false
171
172examples:
173  - |
174    #include <dt-bindings/interrupt-controller/arm-gic.h>
175    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
176    #include <dt-bindings/power/qcom-rpmpd.h>
177
178    displayport-controller@ae90000 {
179        compatible = "qcom,sc7180-dp";
180        reg = <0xae90000 0x200>,
181              <0xae90200 0x200>,
182              <0xae90400 0xc00>,
183              <0xae91000 0x400>,
184              <0xae91400 0x400>;
185        interrupt-parent = <&mdss>;
186        interrupts = <12>;
187        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
188                 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
189                 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
190                 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
191                 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
192        clock-names = "core_iface", "core_aux",
193                      "ctrl_link",
194                      "ctrl_link_iface", "stream_pixel";
195
196        assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
197                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
198
199        assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
200
201        phys = <&dp_phy>;
202        phy-names = "dp";
203
204        #sound-dai-cells = <0>;
205
206        power-domains = <&rpmhpd SC7180_CX>;
207
208        ports {
209            #address-cells = <1>;
210            #size-cells = <0>;
211
212            port@0 {
213                reg = <0>;
214                endpoint {
215                    remote-endpoint = <&dpu_intf0_out>;
216                };
217            };
218
219            port@1 {
220                reg = <1>;
221                endpoint {
222                    remote-endpoint = <&typec>;
223                    data-lanes = <0 1>;
224                    link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
225                };
226            };
227        };
228    };
229...
230