1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MSM Display Port Controller
8
9maintainers:
10  - Kuogee Hsieh <quic_khsieh@quicinc.com>
11
12description: |
13  Device tree bindings for DisplayPort host controller for MSM targets
14  that are compatible with VESA DisplayPort interface specification.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sc7180-dp
20      - qcom,sc7280-dp
21      - qcom,sc7280-edp
22      - qcom,sc8180x-dp
23      - qcom,sc8180x-edp
24      - qcom,sm8350-dp
25
26  reg:
27    minItems: 4
28    items:
29      - description: ahb register block
30      - description: aux register block
31      - description: link register block
32      - description: p0 register block
33      - description: p1 register block
34
35  interrupts:
36    maxItems: 1
37
38  clocks:
39    items:
40      - description: AHB clock to enable register access
41      - description: Display Port AUX clock
42      - description: Display Port Link clock
43      - description: Link interface clock between DP and PHY
44      - description: Display Port Pixel clock
45
46  clock-names:
47    items:
48      - const: core_iface
49      - const: core_aux
50      - const: ctrl_link
51      - const: ctrl_link_iface
52      - const: stream_pixel
53
54  assigned-clocks:
55    items:
56      - description: link clock source
57      - description: pixel clock source
58
59  assigned-clock-parents:
60    items:
61      - description: phy 0 parent
62      - description: phy 1 parent
63
64  phys:
65    maxItems: 1
66
67  phy-names:
68    items:
69      - const: dp
70
71  operating-points-v2: true
72
73  opp-table: true
74
75  power-domains:
76    maxItems: 1
77
78  aux-bus:
79    $ref: /schemas/display/dp-aux-bus.yaml#
80
81  data-lanes:
82    $ref: /schemas/types.yaml#/definitions/uint32-array
83    minItems: 1
84    maxItems: 4
85    items:
86      maximum: 3
87
88  "#sound-dai-cells":
89    const: 0
90
91  vdda-0p9-supply:
92    deprecated: true
93  vdda-1p2-supply:
94    deprecated: true
95
96  ports:
97    $ref: /schemas/graph.yaml#/properties/ports
98    properties:
99      port@0:
100        $ref: /schemas/graph.yaml#/properties/port
101        description: Input endpoint of the controller
102
103      port@1:
104        $ref: /schemas/graph.yaml#/properties/port
105        description: Output endpoint of the controller
106
107required:
108  - compatible
109  - reg
110  - interrupts
111  - clocks
112  - clock-names
113  - phys
114  - phy-names
115  - power-domains
116  - ports
117
118allOf:
119  # AUX BUS does not exist on DP controllers
120  # Audio output also is present only on DP output
121  # p1 regions is present on DP, but not on eDP
122  - if:
123      properties:
124        compatible:
125          contains:
126            enum:
127              - qcom,sc7280-edp
128              - qcom,sc8180x-edp
129    then:
130      properties:
131        "#sound-dai-cells": false
132        reg:
133          maxItems: 4
134    else:
135      properties:
136        aux-bus: false
137        reg:
138          minItems: 5
139      required:
140        - "#sound-dai-cells"
141
142additionalProperties: false
143
144examples:
145  - |
146    #include <dt-bindings/interrupt-controller/arm-gic.h>
147    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
148    #include <dt-bindings/power/qcom-rpmpd.h>
149
150    displayport-controller@ae90000 {
151        compatible = "qcom,sc7180-dp";
152        reg = <0xae90000 0x200>,
153              <0xae90200 0x200>,
154              <0xae90400 0xc00>,
155              <0xae91000 0x400>,
156              <0xae91400 0x400>;
157        interrupt-parent = <&mdss>;
158        interrupts = <12>;
159        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
160                 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
161                 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
162                 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
163                 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
164        clock-names = "core_iface", "core_aux",
165                      "ctrl_link",
166                      "ctrl_link_iface", "stream_pixel";
167
168        assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
169                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
170
171        assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
172
173        phys = <&dp_phy>;
174        phy-names = "dp";
175
176        #sound-dai-cells = <0>;
177
178        power-domains = <&rpmhpd SC7180_CX>;
179
180        ports {
181            #address-cells = <1>;
182            #size-cells = <0>;
183
184            port@0 {
185                reg = <0>;
186                endpoint {
187                    remote-endpoint = <&dpu_intf0_out>;
188                };
189            };
190
191            port@1 {
192                reg = <1>;
193                endpoint {
194                    remote-endpoint = <&typec>;
195                };
196            };
197        };
198    };
199...
200