1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MSM Display Port Controller
8
9maintainers:
10  - Kuogee Hsieh <quic_khsieh@quicinc.com>
11
12description: |
13  Device tree bindings for DisplayPort host controller for MSM targets
14  that are compatible with VESA DisplayPort interface specification.
15
16properties:
17  compatible:
18    enum:
19      - qcom,sc7180-dp
20      - qcom,sc7280-dp
21      - qcom,sc7280-edp
22      - qcom,sc8180x-dp
23      - qcom,sc8180x-edp
24      - qcom,sc8280xp-dp
25      - qcom,sc8280xp-edp
26      - qcom,sdm845-dp
27      - qcom,sm8350-dp
28
29  reg:
30    minItems: 4
31    items:
32      - description: ahb register block
33      - description: aux register block
34      - description: link register block
35      - description: p0 register block
36      - description: p1 register block
37
38  interrupts:
39    maxItems: 1
40
41  clocks:
42    items:
43      - description: AHB clock to enable register access
44      - description: Display Port AUX clock
45      - description: Display Port Link clock
46      - description: Link interface clock between DP and PHY
47      - description: Display Port Pixel clock
48
49  clock-names:
50    items:
51      - const: core_iface
52      - const: core_aux
53      - const: ctrl_link
54      - const: ctrl_link_iface
55      - const: stream_pixel
56
57  assigned-clocks:
58    items:
59      - description: link clock source
60      - description: pixel clock source
61
62  assigned-clock-parents:
63    items:
64      - description: phy 0 parent
65      - description: phy 1 parent
66
67  phys:
68    maxItems: 1
69
70  phy-names:
71    items:
72      - const: dp
73
74  operating-points-v2:
75    maxItems: 1
76
77  opp-table: true
78
79  power-domains:
80    maxItems: 1
81
82  aux-bus:
83    $ref: /schemas/display/dp-aux-bus.yaml#
84
85  data-lanes:
86    $ref: /schemas/types.yaml#/definitions/uint32-array
87    deprecated: true
88    minItems: 1
89    maxItems: 4
90    items:
91      maximum: 3
92
93  "#sound-dai-cells":
94    const: 0
95
96  vdda-0p9-supply:
97    deprecated: true
98  vdda-1p2-supply:
99    deprecated: true
100
101  ports:
102    $ref: /schemas/graph.yaml#/properties/ports
103    properties:
104      port@0:
105        $ref: /schemas/graph.yaml#/properties/port
106        description: Input endpoint of the controller
107
108      port@1:
109        $ref: /schemas/graph.yaml#/$defs/port-base
110        description: Output endpoint of the controller
111        properties:
112          endpoint:
113            $ref: /schemas/media/video-interfaces.yaml#
114            unevaluatedProperties: false
115            properties:
116              data-lanes:
117                minItems: 1
118                maxItems: 4
119                items:
120                  enum: [ 0, 1, 2, 3 ]
121
122              link-frequencies:
123                minItems: 1
124                maxItems: 4
125                items:
126                  enum: [ 1620000000, 2700000000, 5400000000, 8100000000 ]
127
128    required:
129      - port@0
130      - port@1
131
132required:
133  - compatible
134  - reg
135  - interrupts
136  - clocks
137  - clock-names
138  - phys
139  - phy-names
140  - power-domains
141  - ports
142
143allOf:
144  # AUX BUS does not exist on DP controllers
145  # Audio output also is present only on DP output
146  # p1 regions is present on DP, but not on eDP
147  - if:
148      properties:
149        compatible:
150          contains:
151            enum:
152              - qcom,sc7280-edp
153              - qcom,sc8180x-edp
154              - qcom,sc8280xp-edp
155    then:
156      properties:
157        "#sound-dai-cells": false
158    else:
159      properties:
160        aux-bus: false
161        reg:
162          minItems: 5
163      required:
164        - "#sound-dai-cells"
165
166additionalProperties: false
167
168examples:
169  - |
170    #include <dt-bindings/interrupt-controller/arm-gic.h>
171    #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
172    #include <dt-bindings/power/qcom-rpmpd.h>
173
174    displayport-controller@ae90000 {
175        compatible = "qcom,sc7180-dp";
176        reg = <0xae90000 0x200>,
177              <0xae90200 0x200>,
178              <0xae90400 0xc00>,
179              <0xae91000 0x400>,
180              <0xae91400 0x400>;
181        interrupt-parent = <&mdss>;
182        interrupts = <12>;
183        clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
184                 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
185                 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
186                 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
187                 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
188        clock-names = "core_iface", "core_aux",
189                      "ctrl_link",
190                      "ctrl_link_iface", "stream_pixel";
191
192        assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
193                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
194
195        assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
196
197        phys = <&dp_phy>;
198        phy-names = "dp";
199
200        #sound-dai-cells = <0>;
201
202        power-domains = <&rpmhpd SC7180_CX>;
203
204        ports {
205            #address-cells = <1>;
206            #size-cells = <0>;
207
208            port@0 {
209                reg = <0>;
210                endpoint {
211                    remote-endpoint = <&dpu_intf0_out>;
212                };
213            };
214
215            port@1 {
216                reg = <1>;
217                endpoint {
218                    remote-endpoint = <&typec>;
219                    data-lanes = <0 1>;
220                    link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
221                };
222            };
223        };
224    };
225...
226