1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display overlay
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display overlay, namely OVL, can do alpha blending from
15  the memory.
16  OVL device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - items:
25          - const: mediatek,mt2701-disp-ovl
26      - items:
27          - const: mediatek,mt8173-disp-ovl
28      - items:
29          - const: mediatek,mt8183-disp-ovl
30      - items:
31          - const: mediatek,mt8192-disp-ovl
32      - items:
33          - enum:
34              - mediatek,mt7623-disp-ovl
35              - mediatek,mt2712-disp-ovl
36          - enum:
37              - mediatek,mt2701-disp-ovl
38      - items:
39          - enum:
40              - mediatek,mt8195-disp-ovl
41          - enum:
42              - mediatek,mt8183-disp-ovl
43
44  reg:
45    maxItems: 1
46
47  interrupts:
48    maxItems: 1
49
50  power-domains:
51    description: A phandle and PM domain specifier as defined by bindings of
52      the power controller specified by phandle. See
53      Documentation/devicetree/bindings/power/power-domain.yaml for details.
54
55  clocks:
56    items:
57      - description: OVL Clock
58
59  iommus:
60    description:
61      This property should point to the respective IOMMU block with master port as argument,
62      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
63
64  mediatek,larb:
65    description:
66      This property should contain a phandle pointing to the local arbiter devices defined in
67      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
68      It must sort according to the local arbiter index, like larb0, larb1, larb2...
69    $ref: /schemas/types.yaml#/definitions/phandle-array
70    minItems: 1
71    maxItems: 32
72
73  mediatek,gce-client-reg:
74    description: The register of client driver can be configured by gce with
75      4 arguments defined in this property, such as phandle of gce, subsys id,
76      register offset and size. Each GCE subsys id is mapping to a client
77      defined in the header include/dt-bindings/gce/<chip>-gce.h.
78    $ref: /schemas/types.yaml#/definitions/phandle-array
79    maxItems: 1
80
81required:
82  - compatible
83  - reg
84  - interrupts
85  - power-domains
86  - clocks
87  - iommu
88
89additionalProperties: false
90
91examples:
92  - |
93
94    ovl0: ovl@1400c000 {
95        compatible = "mediatek,mt8173-disp-ovl";
96        reg = <0 0x1400c000 0 0x1000>;
97        interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
98        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
99        clocks = <&mmsys CLK_MM_DISP_OVL0>;
100        iommus = <&iommu M4U_PORT_DISP_OVL0>;
101        mediatek,larb = <&larb0>;
102        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
103    };
104