1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display merge
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display merge, namely MERGE, is used to merge two slice-per-line
15  inputs into one side-by-side output.
16  MERGE device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - items:
25          - const: mediatek,mt8173-disp-merge
26      - items:
27          - const: mediatek,mt8195-disp-merge
28
29  reg:
30    maxItems: 1
31
32  interrupts:
33    maxItems: 1
34
35  power-domains:
36    description: A phandle and PM domain specifier as defined by bindings of
37      the power controller specified by phandle. See
38      Documentation/devicetree/bindings/power/power-domain.yaml for details.
39
40  clocks:
41    maxItems: 2
42    items:
43      - description: MERGE Clock
44      - description: MERGE Async Clock
45          Controlling the synchronous process between MERGE and other display
46          function blocks cross clock domain.
47
48  clock-names:
49    maxItems: 2
50    items:
51      - const: merge
52      - const: merge_async
53
54  mediatek,merge-fifo-en:
55    description:
56      The setting of merge fifo is mainly provided for the display latency
57      buffer to ensure that the back-end panel display data will not be
58      underrun, a little more data is needed in the fifo.
59      According to the merge fifo settings, when the water level is detected
60      to be insufficient, it will trigger RDMA sending ultra and preulra
61      command to SMI to speed up the data rate.
62    type: boolean
63
64  mediatek,merge-mute:
65    description: Support mute function. Mute the content of merge output.
66    type: boolean
67
68  mediatek,gce-client-reg:
69    description: The register of client driver can be configured by gce with
70      4 arguments defined in this property, such as phandle of gce, subsys id,
71      register offset and size. Each GCE subsys id is mapping to a client
72      defined in the header include/dt-bindings/gce/<chip>-gce.h.
73    $ref: /schemas/types.yaml#/definitions/phandle-array
74    maxItems: 1
75
76  resets:
77    description: reset controller
78      See Documentation/devicetree/bindings/reset/reset.txt for details.
79    maxItems: 1
80
81required:
82  - compatible
83  - reg
84  - power-domains
85  - clocks
86
87additionalProperties: false
88
89examples:
90  - |
91
92    merge@14017000 {
93        compatible = "mediatek,mt8173-disp-merge";
94        reg = <0 0x14017000 0 0x1000>;
95        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
96        clocks = <&mmsys CLK_MM_DISP_MERGE>;
97    };
98
99    merge5: disp_vpp_merge5@1c110000 {
100        compatible = "mediatek,mt8195-disp-merge";
101        reg = <0 0x1c110000 0 0x1000>;
102        interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
103        clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
104                 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
105        clock-names = "merge","merge_async";
106        power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
107        mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
108        mediatek,merge-fifo-en = <1>;
109        resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
110    };
111