1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek Ethdr Device Tree Bindings
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  ETHDR is designed for HDR video and graphics conversion in the external display path.
15  It handles multiple HDR input types and performs tone mapping, color space/color
16  format conversion, and then combine different layers, output the required HDR or
17  SDR signal to the subsequent display path. This engine is composed of two video
18  frontends, two graphic frontends, one video backend and a mixer. ETHDR has two
19  DMA function blocks, DS and ADL. These two function blocks read the pre-programmed
20  registers from DRAM and set them to HW in the v-blanking period.
21
22properties:
23  compatible:
24    items:
25      - const: mediatek,mt8195-disp-ethdr
26  reg:
27    maxItems: 7
28  reg-names:
29    items:
30      - const: mixer
31      - const: vdo_fe0
32      - const: vdo_fe1
33      - const: gfx_fe0
34      - const: gfx_fe1
35      - const: vdo_be
36      - const: adl_ds
37  interrupts:
38    minItems: 1
39  iommus:
40    description: The compatible property is DMA function blocks.
41      Should point to the respective IOMMU block with master port as argument,
42      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
43      details.
44    minItems: 1
45    maxItems: 2
46  clocks:
47    items:
48      - description: mixer clock
49      - description: video frontend 0 clock
50      - description: video frontend 1 clock
51      - description: graphic frontend 0 clock
52      - description: graphic frontend 1 clock
53      - description: video backend clock
54      - description: autodownload and menuload clock
55      - description: video frontend 0 async clock
56      - description: video frontend 1 async clock
57      - description: graphic frontend 0 async clock
58      - description: graphic frontend 1 async clock
59      - description: video backend async clock
60      - description: ethdr top clock
61  clock-names:
62    items:
63      - const: mixer
64      - const: vdo_fe0
65      - const: vdo_fe1
66      - const: gfx_fe0
67      - const: gfx_fe1
68      - const: vdo_be
69      - const: adl_ds
70      - const: vdo_fe0_async
71      - const: vdo_fe1_async
72      - const: gfx_fe0_async
73      - const: gfx_fe1_async
74      - const: vdo_be_async
75      - const: ethdr_top
76  power-domains:
77    maxItems: 1
78  resets:
79    maxItems: 5
80  mediatek,gce-client-reg:
81    $ref: /schemas/types.yaml#/definitions/phandle-array
82    description: The register of display function block to be set by gce.
83      There are 4 arguments in this property, gce node, subsys id, offset and
84      register size. The subsys id is defined in the gce header of each chips
85      include/include/dt-bindings/gce/<chip>-gce.h, mapping to the register of
86      display function block.
87
88required:
89  - compatible
90  - reg
91  - clocks
92  - clock-names
93  - interrupts
94  - power-domains
95
96additionalProperties: false
97
98examples:
99  - |
100
101    disp_ethdr@1c114000 {
102            compatible = "mediatek,mt8195-disp-ethdr";
103            reg = <0 0x1c114000 0 0x1000>,
104                  <0 0x1c115000 0 0x1000>,
105                  <0 0x1c117000 0 0x1000>,
106                  <0 0x1c119000 0 0x1000>,
107                  <0 0x1c11A000 0 0x1000>,
108                  <0 0x1c11B000 0 0x1000>,
109                  <0 0x1c11C000 0 0x1000>;
110            reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
111                        "vdo_be", "adl_ds";
112            mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
113                                      <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
114                                      <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
115                                      <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
116                                      <&gce0 SUBSYS_1c11XXXX 0xA000 0x1000>,
117                                      <&gce0 SUBSYS_1c11XXXX 0xB000 0x1000>,
118                                      <&gce0 SUBSYS_1c11XXXX 0xC000 0x1000>;
119            clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
120                     <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
121                     <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
122                     <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
123                     <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
124                     <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
125                     <&vdosys1 CLK_VDO1_26M_SLOW>,
126                     <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
127                     <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
128                     <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
129                     <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
130                     <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
131                     <&topckgen CLK_TOP_ETHDR_SEL>;
132            clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
133                          "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
134                          "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
135                          "ethdr_top";
136            power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
137            iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
138                     <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
139            interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
140            resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
141                     <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
142                     <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
143                     <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
144                     <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
145    };
146
147...
148