1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: mediatek DPI Controller Device Tree Bindings 8 9maintainers: 10 - CK Hu <ck.hu@mediatek.com> 11 - Jitao shi <jitao.shi@mediatek.com> 12 13description: | 14 The Mediatek DPI function block is a sink of the display subsystem and 15 provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel 16 output bus. 17 18properties: 19 compatible: 20 enum: 21 - mediatek,mt2701-dpi 22 - mediatek,mt7623-dpi 23 - mediatek,mt8173-dpi 24 - mediatek,mt8183-dpi 25 - mediatek,mt8186-dpi 26 - mediatek,mt8192-dpi 27 28 reg: 29 maxItems: 1 30 31 interrupts: 32 maxItems: 1 33 34 clocks: 35 items: 36 - description: Pixel Clock 37 - description: Engine Clock 38 - description: DPI PLL 39 40 clock-names: 41 items: 42 - const: pixel 43 - const: engine 44 - const: pll 45 46 pinctrl-0: true 47 pinctrl-1: true 48 49 pinctrl-names: 50 items: 51 - const: default 52 - const: sleep 53 54 port: 55 $ref: /schemas/graph.yaml#/properties/port 56 description: 57 Output port node. This port should be connected to the input port of an 58 attached HDMI or LVDS encoder chip. 59 60required: 61 - compatible 62 - reg 63 - interrupts 64 - clocks 65 - clock-names 66 - port 67 68additionalProperties: false 69 70examples: 71 - | 72 #include <dt-bindings/interrupt-controller/arm-gic.h> 73 #include <dt-bindings/clock/mt8173-clk.h> 74 75 dpi0: dpi@1401d000 { 76 compatible = "mediatek,mt8173-dpi"; 77 reg = <0x1401d000 0x1000>; 78 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 79 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 80 <&mmsys CLK_MM_DPI_ENGINE>, 81 <&apmixedsys CLK_APMIXED_TVDPLL>; 82 clock-names = "pixel", "engine", "pll"; 83 pinctrl-names = "default", "sleep"; 84 pinctrl-0 = <&dpi_pin_func>; 85 pinctrl-1 = <&dpi_pin_idle>; 86 87 port { 88 dpi0_out: endpoint { 89 remote-endpoint = <&hdmi0_in>; 90 }; 91 }; 92 }; 93 94... 95