14ed545e7Sjason-jh.lin# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
24ed545e7Sjason-jh.lin%YAML 1.2
34ed545e7Sjason-jh.lin---
44ed545e7Sjason-jh.lin$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
54ed545e7Sjason-jh.lin$schema: http://devicetree.org/meta-schemas/core.yaml#
64ed545e7Sjason-jh.lin
74ed545e7Sjason-jh.lintitle: Mediatek display overlay
84ed545e7Sjason-jh.lin
94ed545e7Sjason-jh.linmaintainers:
104ed545e7Sjason-jh.lin  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
114ed545e7Sjason-jh.lin  - Philipp Zabel <p.zabel@pengutronix.de>
124ed545e7Sjason-jh.lin
134ed545e7Sjason-jh.lindescription: |
144ed545e7Sjason-jh.lin  Mediatek display overlay, namely OVL, can do alpha blending from
154ed545e7Sjason-jh.lin  the memory.
164ed545e7Sjason-jh.lin  OVL device node must be siblings to the central MMSYS_CONFIG node.
174ed545e7Sjason-jh.lin  For a description of the MMSYS_CONFIG binding, see
184ed545e7Sjason-jh.lin  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
194ed545e7Sjason-jh.lin  for details.
204ed545e7Sjason-jh.lin
214ed545e7Sjason-jh.linproperties:
224ed545e7Sjason-jh.lin  compatible:
234ed545e7Sjason-jh.lin    oneOf:
244ed545e7Sjason-jh.lin      - items:
254ed545e7Sjason-jh.lin          - const: mediatek,mt2701-disp-ovl
264ed545e7Sjason-jh.lin      - items:
274ed545e7Sjason-jh.lin          - const: mediatek,mt8173-disp-ovl
284ed545e7Sjason-jh.lin      - items:
294ed545e7Sjason-jh.lin          - const: mediatek,mt8183-disp-ovl
304ed545e7Sjason-jh.lin      - items:
314ed545e7Sjason-jh.lin          - const: mediatek,mt8192-disp-ovl
324ed545e7Sjason-jh.lin      - items:
334ed545e7Sjason-jh.lin          - enum:
344ed545e7Sjason-jh.lin              - mediatek,mt7623-disp-ovl
354ed545e7Sjason-jh.lin              - mediatek,mt2712-disp-ovl
3646bc0d98SRex-BC Chen          - const: mediatek,mt2701-disp-ovl
37a79257baSjason-jh.lin      - items:
38a79257baSjason-jh.lin          - enum:
39a79257baSjason-jh.lin              - mediatek,mt8195-disp-ovl
4046bc0d98SRex-BC Chen          - const: mediatek,mt8183-disp-ovl
41*8a26ea19SRex-BC Chen      - items:
42*8a26ea19SRex-BC Chen          - enum:
43*8a26ea19SRex-BC Chen              - mediatek,mt8186-disp-ovl
44*8a26ea19SRex-BC Chen          - const: mediatek,mt8192-disp-ovl
454ed545e7Sjason-jh.lin
464ed545e7Sjason-jh.lin  reg:
474ed545e7Sjason-jh.lin    maxItems: 1
484ed545e7Sjason-jh.lin
494ed545e7Sjason-jh.lin  interrupts:
504ed545e7Sjason-jh.lin    maxItems: 1
514ed545e7Sjason-jh.lin
524ed545e7Sjason-jh.lin  power-domains:
534ed545e7Sjason-jh.lin    description: A phandle and PM domain specifier as defined by bindings of
544ed545e7Sjason-jh.lin      the power controller specified by phandle. See
554ed545e7Sjason-jh.lin      Documentation/devicetree/bindings/power/power-domain.yaml for details.
564ed545e7Sjason-jh.lin
574ed545e7Sjason-jh.lin  clocks:
584ed545e7Sjason-jh.lin    items:
594ed545e7Sjason-jh.lin      - description: OVL Clock
604ed545e7Sjason-jh.lin
614ed545e7Sjason-jh.lin  iommus:
624ed545e7Sjason-jh.lin    description:
634ed545e7Sjason-jh.lin      This property should point to the respective IOMMU block with master port as argument,
644ed545e7Sjason-jh.lin      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
654ed545e7Sjason-jh.lin
664ed545e7Sjason-jh.lin  mediatek,gce-client-reg:
674ed545e7Sjason-jh.lin    description: The register of client driver can be configured by gce with
684ed545e7Sjason-jh.lin      4 arguments defined in this property, such as phandle of gce, subsys id,
694ed545e7Sjason-jh.lin      register offset and size. Each GCE subsys id is mapping to a client
704ed545e7Sjason-jh.lin      defined in the header include/dt-bindings/gce/<chip>-gce.h.
714ed545e7Sjason-jh.lin    $ref: /schemas/types.yaml#/definitions/phandle-array
724ed545e7Sjason-jh.lin    maxItems: 1
734ed545e7Sjason-jh.lin
744ed545e7Sjason-jh.linrequired:
754ed545e7Sjason-jh.lin  - compatible
764ed545e7Sjason-jh.lin  - reg
774ed545e7Sjason-jh.lin  - interrupts
784ed545e7Sjason-jh.lin  - power-domains
794ed545e7Sjason-jh.lin  - clocks
8010f17b20SAngeloGioacchino Del Regno  - iommus
814ed545e7Sjason-jh.lin
824ed545e7Sjason-jh.linadditionalProperties: false
834ed545e7Sjason-jh.lin
844ed545e7Sjason-jh.linexamples:
854ed545e7Sjason-jh.lin  - |
86bff4e302SAngeloGioacchino Del Regno    #include <dt-bindings/interrupt-controller/arm-gic.h>
87bff4e302SAngeloGioacchino Del Regno    #include <dt-bindings/clock/mt8173-clk.h>
88bff4e302SAngeloGioacchino Del Regno    #include <dt-bindings/power/mt8173-power.h>
89bff4e302SAngeloGioacchino Del Regno    #include <dt-bindings/gce/mt8173-gce.h>
90bff4e302SAngeloGioacchino Del Regno    #include <dt-bindings/memory/mt8173-larb-port.h>
91bff4e302SAngeloGioacchino Del Regno
92bff4e302SAngeloGioacchino Del Regno    soc {
93bff4e302SAngeloGioacchino Del Regno        #address-cells = <2>;
94bff4e302SAngeloGioacchino Del Regno        #size-cells = <2>;
954ed545e7Sjason-jh.lin
964ed545e7Sjason-jh.lin        ovl0: ovl@1400c000 {
974ed545e7Sjason-jh.lin            compatible = "mediatek,mt8173-disp-ovl";
984ed545e7Sjason-jh.lin            reg = <0 0x1400c000 0 0x1000>;
994ed545e7Sjason-jh.lin            interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
1004ed545e7Sjason-jh.lin            power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1014ed545e7Sjason-jh.lin            clocks = <&mmsys CLK_MM_DISP_OVL0>;
1024ed545e7Sjason-jh.lin            iommus = <&iommu M4U_PORT_DISP_OVL0>;
1034ed545e7Sjason-jh.lin            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1044ed545e7Sjason-jh.lin        };
105bff4e302SAngeloGioacchino Del Regno    };
106