1*e201c963SNancy.Lin# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*e201c963SNancy.Lin%YAML 1.2 3*e201c963SNancy.Lin--- 4*e201c963SNancy.Lin$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml# 5*e201c963SNancy.Lin$schema: http://devicetree.org/meta-schemas/core.yaml# 6*e201c963SNancy.Lin 7*e201c963SNancy.Lintitle: MediaTek MDP RDMA 8*e201c963SNancy.Lin 9*e201c963SNancy.Linmaintainers: 10*e201c963SNancy.Lin - Chun-Kuang Hu <chunkuang.hu@kernel.org> 11*e201c963SNancy.Lin - Philipp Zabel <p.zabel@pengutronix.de> 12*e201c963SNancy.Lin 13*e201c963SNancy.Lindescription: 14*e201c963SNancy.Lin The MediaTek MDP RDMA stands for Read Direct Memory Access. 15*e201c963SNancy.Lin It provides real time data to the back-end panel driver, such as DSI, 16*e201c963SNancy.Lin DPI and DP_INTF. 17*e201c963SNancy.Lin It contains one line buffer to store the sufficient pixel data. 18*e201c963SNancy.Lin RDMA device node must be siblings to the central MMSYS_CONFIG node. 19*e201c963SNancy.Lin For a description of the MMSYS_CONFIG binding, see 20*e201c963SNancy.Lin Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details. 21*e201c963SNancy.Lin 22*e201c963SNancy.Linproperties: 23*e201c963SNancy.Lin compatible: 24*e201c963SNancy.Lin const: mediatek,mt8195-vdo1-rdma 25*e201c963SNancy.Lin 26*e201c963SNancy.Lin reg: 27*e201c963SNancy.Lin maxItems: 1 28*e201c963SNancy.Lin 29*e201c963SNancy.Lin interrupts: 30*e201c963SNancy.Lin maxItems: 1 31*e201c963SNancy.Lin 32*e201c963SNancy.Lin power-domains: 33*e201c963SNancy.Lin maxItems: 1 34*e201c963SNancy.Lin 35*e201c963SNancy.Lin clocks: 36*e201c963SNancy.Lin items: 37*e201c963SNancy.Lin - description: RDMA Clock 38*e201c963SNancy.Lin 39*e201c963SNancy.Lin iommus: 40*e201c963SNancy.Lin maxItems: 1 41*e201c963SNancy.Lin 42*e201c963SNancy.Lin mediatek,gce-client-reg: 43*e201c963SNancy.Lin description: 44*e201c963SNancy.Lin The register of display function block to be set by gce. There are 4 arguments, 45*e201c963SNancy.Lin such as gce node, subsys id, offset and register size. The subsys id that is 46*e201c963SNancy.Lin mapping to the register of display function blocks is defined in the gce header 47*e201c963SNancy.Lin include/dt-bindings/gce/<chip>-gce.h of each chips. 48*e201c963SNancy.Lin $ref: /schemas/types.yaml#/definitions/phandle-array 49*e201c963SNancy.Lin items: 50*e201c963SNancy.Lin items: 51*e201c963SNancy.Lin - description: phandle of GCE 52*e201c963SNancy.Lin - description: GCE subsys id 53*e201c963SNancy.Lin - description: register offset 54*e201c963SNancy.Lin - description: register size 55*e201c963SNancy.Lin maxItems: 1 56*e201c963SNancy.Lin 57*e201c963SNancy.Linrequired: 58*e201c963SNancy.Lin - compatible 59*e201c963SNancy.Lin - reg 60*e201c963SNancy.Lin - power-domains 61*e201c963SNancy.Lin - clocks 62*e201c963SNancy.Lin - iommus 63*e201c963SNancy.Lin - mediatek,gce-client-reg 64*e201c963SNancy.Lin 65*e201c963SNancy.LinadditionalProperties: false 66*e201c963SNancy.Lin 67*e201c963SNancy.Linexamples: 68*e201c963SNancy.Lin - | 69*e201c963SNancy.Lin #include <dt-bindings/interrupt-controller/arm-gic.h> 70*e201c963SNancy.Lin #include <dt-bindings/clock/mt8195-clk.h> 71*e201c963SNancy.Lin #include <dt-bindings/power/mt8195-power.h> 72*e201c963SNancy.Lin #include <dt-bindings/gce/mt8195-gce.h> 73*e201c963SNancy.Lin #include <dt-bindings/memory/mt8195-memory-port.h> 74*e201c963SNancy.Lin 75*e201c963SNancy.Lin soc { 76*e201c963SNancy.Lin #address-cells = <2>; 77*e201c963SNancy.Lin #size-cells = <2>; 78*e201c963SNancy.Lin 79*e201c963SNancy.Lin rdma@1c104000 { 80*e201c963SNancy.Lin compatible = "mediatek,mt8195-vdo1-rdma"; 81*e201c963SNancy.Lin reg = <0 0x1c104000 0 0x1000>; 82*e201c963SNancy.Lin interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; 83*e201c963SNancy.Lin clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; 84*e201c963SNancy.Lin power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 85*e201c963SNancy.Lin iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; 86*e201c963SNancy.Lin mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; 87*e201c963SNancy.Lin }; 88*e201c963SNancy.Lin }; 89