122ffb89eSXinlei Lee# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 222ffb89eSXinlei Lee%YAML 1.2 322ffb89eSXinlei Lee--- 422ffb89eSXinlei Lee$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml# 522ffb89eSXinlei Lee$schema: http://devicetree.org/meta-schemas/core.yaml# 622ffb89eSXinlei Lee 7*a612130cSKrzysztof Kozlowskititle: MediaTek DSI Controller 822ffb89eSXinlei Lee 922ffb89eSXinlei Leemaintainers: 1022ffb89eSXinlei Lee - Chun-Kuang Hu <chunkuang.hu@kernel.org> 1122ffb89eSXinlei Lee - Philipp Zabel <p.zabel@pengutronix.de> 1222ffb89eSXinlei Lee - Jitao Shi <jitao.shi@mediatek.com> 1322ffb89eSXinlei Lee - Xinlei Lee <xinlei.lee@mediatek.com> 1422ffb89eSXinlei Lee 1522ffb89eSXinlei Leedescription: | 1622ffb89eSXinlei Lee The MediaTek DSI function block is a sink of the display subsystem and can 1722ffb89eSXinlei Lee drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- 1822ffb89eSXinlei Lee channel output. 1922ffb89eSXinlei Lee 2022ffb89eSXinlei LeeallOf: 2122ffb89eSXinlei Lee - $ref: /schemas/display/dsi-controller.yaml# 2222ffb89eSXinlei Lee 2322ffb89eSXinlei Leeproperties: 2422ffb89eSXinlei Lee compatible: 2522ffb89eSXinlei Lee enum: 2622ffb89eSXinlei Lee - mediatek,mt2701-dsi 2722ffb89eSXinlei Lee - mediatek,mt7623-dsi 2822ffb89eSXinlei Lee - mediatek,mt8167-dsi 2922ffb89eSXinlei Lee - mediatek,mt8173-dsi 3022ffb89eSXinlei Lee - mediatek,mt8183-dsi 31f7fe4264SXinlei Lee - mediatek,mt8186-dsi 3222ffb89eSXinlei Lee 3322ffb89eSXinlei Lee reg: 3422ffb89eSXinlei Lee maxItems: 1 3522ffb89eSXinlei Lee 3622ffb89eSXinlei Lee interrupts: 3722ffb89eSXinlei Lee maxItems: 1 3822ffb89eSXinlei Lee 3922ffb89eSXinlei Lee power-domains: 4022ffb89eSXinlei Lee maxItems: 1 4122ffb89eSXinlei Lee 4222ffb89eSXinlei Lee clocks: 4322ffb89eSXinlei Lee items: 4422ffb89eSXinlei Lee - description: Engine Clock 4522ffb89eSXinlei Lee - description: Digital Clock 4622ffb89eSXinlei Lee - description: HS Clock 4722ffb89eSXinlei Lee 4822ffb89eSXinlei Lee clock-names: 4922ffb89eSXinlei Lee items: 5022ffb89eSXinlei Lee - const: engine 5122ffb89eSXinlei Lee - const: digital 5222ffb89eSXinlei Lee - const: hs 5322ffb89eSXinlei Lee 5422ffb89eSXinlei Lee resets: 5522ffb89eSXinlei Lee maxItems: 1 5622ffb89eSXinlei Lee 5722ffb89eSXinlei Lee phys: 5822ffb89eSXinlei Lee maxItems: 1 5922ffb89eSXinlei Lee 6022ffb89eSXinlei Lee phy-names: 6122ffb89eSXinlei Lee items: 6222ffb89eSXinlei Lee - const: dphy 6322ffb89eSXinlei Lee 6422ffb89eSXinlei Lee port: 6522ffb89eSXinlei Lee $ref: /schemas/graph.yaml#/properties/port 6622ffb89eSXinlei Lee description: 6722ffb89eSXinlei Lee Output port node. This port should be connected to the input 6822ffb89eSXinlei Lee port of an attached DSI panel or DSI-to-eDP encoder chip. 6922ffb89eSXinlei Lee 7022ffb89eSXinlei Leerequired: 7122ffb89eSXinlei Lee - compatible 7222ffb89eSXinlei Lee - reg 7322ffb89eSXinlei Lee - interrupts 7422ffb89eSXinlei Lee - power-domains 7522ffb89eSXinlei Lee - clocks 7622ffb89eSXinlei Lee - clock-names 7722ffb89eSXinlei Lee - phys 7822ffb89eSXinlei Lee - phy-names 7922ffb89eSXinlei Lee - port 8022ffb89eSXinlei Lee 8122ffb89eSXinlei LeeunevaluatedProperties: false 8222ffb89eSXinlei Lee 8322ffb89eSXinlei Leeexamples: 8422ffb89eSXinlei Lee - | 8522ffb89eSXinlei Lee #include <dt-bindings/clock/mt8183-clk.h> 8622ffb89eSXinlei Lee #include <dt-bindings/interrupt-controller/arm-gic.h> 8722ffb89eSXinlei Lee #include <dt-bindings/interrupt-controller/irq.h> 8822ffb89eSXinlei Lee #include <dt-bindings/power/mt8183-power.h> 8922ffb89eSXinlei Lee #include <dt-bindings/phy/phy.h> 9022ffb89eSXinlei Lee #include <dt-bindings/reset/mt8183-resets.h> 9122ffb89eSXinlei Lee 9222ffb89eSXinlei Lee soc { 9322ffb89eSXinlei Lee #address-cells = <2>; 9422ffb89eSXinlei Lee #size-cells = <2>; 9522ffb89eSXinlei Lee 9622ffb89eSXinlei Lee dsi0: dsi@14014000 { 9722ffb89eSXinlei Lee compatible = "mediatek,mt8183-dsi"; 9822ffb89eSXinlei Lee reg = <0 0x14014000 0 0x1000>; 9922ffb89eSXinlei Lee interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; 10022ffb89eSXinlei Lee power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 10122ffb89eSXinlei Lee clocks = <&mmsys CLK_MM_DSI0_MM>, 10222ffb89eSXinlei Lee <&mmsys CLK_MM_DSI0_IF>, 10322ffb89eSXinlei Lee <&mipi_tx0>; 10422ffb89eSXinlei Lee clock-names = "engine", "digital", "hs"; 10522ffb89eSXinlei Lee resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; 10622ffb89eSXinlei Lee phys = <&mipi_tx0>; 10722ffb89eSXinlei Lee phy-names = "dphy"; 10822ffb89eSXinlei Lee port { 10922ffb89eSXinlei Lee dsi0_out: endpoint { 11022ffb89eSXinlei Lee remote-endpoint = <&panel_in>; 11122ffb89eSXinlei Lee }; 11222ffb89eSXinlei Lee }; 11322ffb89eSXinlei Lee }; 11422ffb89eSXinlei Lee }; 11522ffb89eSXinlei Lee 11622ffb89eSXinlei Lee... 117