19273cf7dSJitao Shi# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
29273cf7dSJitao Shi%YAML 1.2
39273cf7dSJitao Shi---
49273cf7dSJitao Shi$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
59273cf7dSJitao Shi$schema: http://devicetree.org/meta-schemas/core.yaml#
69273cf7dSJitao Shi
79273cf7dSJitao Shititle: mediatek DPI Controller Device Tree Bindings
89273cf7dSJitao Shi
99273cf7dSJitao Shimaintainers:
109273cf7dSJitao Shi  - CK Hu <ck.hu@mediatek.com>
119273cf7dSJitao Shi  - Jitao shi <jitao.shi@mediatek.com>
129273cf7dSJitao Shi
139273cf7dSJitao Shidescription: |
149273cf7dSJitao Shi  The Mediatek DPI function block is a sink of the display subsystem and
159273cf7dSJitao Shi  provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
169273cf7dSJitao Shi  output bus.
179273cf7dSJitao Shi
189273cf7dSJitao Shiproperties:
199273cf7dSJitao Shi  compatible:
209273cf7dSJitao Shi    enum:
219273cf7dSJitao Shi      - mediatek,mt2701-dpi
229273cf7dSJitao Shi      - mediatek,mt7623-dpi
239273cf7dSJitao Shi      - mediatek,mt8173-dpi
249273cf7dSJitao Shi      - mediatek,mt8183-dpi
25*52136021SXinlei Lee      - mediatek,mt8186-dpi
2661865513SJitao Shi      - mediatek,mt8192-dpi
279273cf7dSJitao Shi
289273cf7dSJitao Shi  reg:
299273cf7dSJitao Shi    maxItems: 1
309273cf7dSJitao Shi
319273cf7dSJitao Shi  interrupts:
329273cf7dSJitao Shi    maxItems: 1
339273cf7dSJitao Shi
349273cf7dSJitao Shi  clocks:
359273cf7dSJitao Shi    items:
369273cf7dSJitao Shi      - description: Pixel Clock
379273cf7dSJitao Shi      - description: Engine Clock
389273cf7dSJitao Shi      - description: DPI PLL
399273cf7dSJitao Shi
409273cf7dSJitao Shi  clock-names:
419273cf7dSJitao Shi    items:
429273cf7dSJitao Shi      - const: pixel
439273cf7dSJitao Shi      - const: engine
449273cf7dSJitao Shi      - const: pll
459273cf7dSJitao Shi
469273cf7dSJitao Shi  pinctrl-0: true
479273cf7dSJitao Shi  pinctrl-1: true
489273cf7dSJitao Shi
499273cf7dSJitao Shi  pinctrl-names:
509273cf7dSJitao Shi    items:
519273cf7dSJitao Shi      - const: default
529273cf7dSJitao Shi      - const: sleep
539273cf7dSJitao Shi
549273cf7dSJitao Shi  port:
55be7507bdSRob Herring    $ref: /schemas/graph.yaml#/properties/port
569273cf7dSJitao Shi    description:
57be7507bdSRob Herring      Output port node. This port should be connected to the input port of an
58be7507bdSRob Herring      attached HDMI or LVDS encoder chip.
599273cf7dSJitao Shi
609273cf7dSJitao Shirequired:
619273cf7dSJitao Shi  - compatible
629273cf7dSJitao Shi  - reg
639273cf7dSJitao Shi  - interrupts
649273cf7dSJitao Shi  - clocks
659273cf7dSJitao Shi  - clock-names
669273cf7dSJitao Shi  - port
679273cf7dSJitao Shi
689273cf7dSJitao ShiadditionalProperties: false
699273cf7dSJitao Shi
709273cf7dSJitao Shiexamples:
719273cf7dSJitao Shi  - |
729273cf7dSJitao Shi    #include <dt-bindings/interrupt-controller/arm-gic.h>
739273cf7dSJitao Shi    #include <dt-bindings/clock/mt8173-clk.h>
74bff4e302SAngeloGioacchino Del Regno
759273cf7dSJitao Shi    dpi0: dpi@1401d000 {
769273cf7dSJitao Shi        compatible = "mediatek,mt8173-dpi";
779273cf7dSJitao Shi        reg = <0x1401d000 0x1000>;
789273cf7dSJitao Shi        interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
799273cf7dSJitao Shi        clocks = <&mmsys CLK_MM_DPI_PIXEL>,
809273cf7dSJitao Shi             <&mmsys CLK_MM_DPI_ENGINE>,
819273cf7dSJitao Shi             <&apmixedsys CLK_APMIXED_TVDPLL>;
829273cf7dSJitao Shi        clock-names = "pixel", "engine", "pll";
839273cf7dSJitao Shi        pinctrl-names = "default", "sleep";
849273cf7dSJitao Shi        pinctrl-0 = <&dpi_pin_func>;
859273cf7dSJitao Shi        pinctrl-1 = <&dpi_pin_idle>;
869273cf7dSJitao Shi
879273cf7dSJitao Shi        port {
889273cf7dSJitao Shi            dpi0_out: endpoint {
899273cf7dSJitao Shi                remote-endpoint = <&hdmi0_in>;
909273cf7dSJitao Shi            };
919273cf7dSJitao Shi        };
929273cf7dSJitao Shi    };
939273cf7dSJitao Shi
949273cf7dSJitao Shi...
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