1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek display color correction
8
9maintainers:
10  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11  - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14  Mediatek display color correction, namely CCORR, reproduces correct color
15  on panels with different color gamut.
16  CCORR device node must be siblings to the central MMSYS_CONFIG node.
17  For a description of the MMSYS_CONFIG binding, see
18  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19  for details.
20
21properties:
22  compatible:
23    oneOf:
24      - items:
25          - const: mediatek,mt8183-disp-ccorr
26      - items:
27          - const: mediatek,mt8192-disp-ccorr
28      - items:
29          - enum:
30              - mediatek,mt8188-disp-ccorr
31              - mediatek,mt8195-disp-ccorr
32          - const: mediatek,mt8192-disp-ccorr
33      - items:
34          - enum:
35              - mediatek,mt8186-disp-ccorr
36          - const: mediatek,mt8183-disp-ccorr
37
38  reg:
39    maxItems: 1
40
41  interrupts:
42    maxItems: 1
43
44  power-domains:
45    description: A phandle and PM domain specifier as defined by bindings of
46      the power controller specified by phandle. See
47      Documentation/devicetree/bindings/power/power-domain.yaml for details.
48
49  clocks:
50    items:
51      - description: CCORR Clock
52
53  mediatek,gce-client-reg:
54    description: The register of client driver can be configured by gce with
55      4 arguments defined in this property, such as phandle of gce, subsys id,
56      register offset and size. Each GCE subsys id is mapping to a client
57      defined in the header include/dt-bindings/gce/<chip>-gce.h.
58    $ref: /schemas/types.yaml#/definitions/phandle-array
59    maxItems: 1
60
61required:
62  - compatible
63  - reg
64  - interrupts
65  - power-domains
66  - clocks
67
68additionalProperties: false
69
70examples:
71  - |
72    #include <dt-bindings/interrupt-controller/arm-gic.h>
73    #include <dt-bindings/clock/mt8183-clk.h>
74    #include <dt-bindings/power/mt8183-power.h>
75    #include <dt-bindings/gce/mt8183-gce.h>
76
77    soc {
78        #address-cells = <2>;
79        #size-cells = <2>;
80
81        ccorr0: ccorr@1400f000 {
82            compatible = "mediatek,mt8183-disp-ccorr";
83            reg = <0 0x1400f000 0 0x1000>;
84            interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
85            power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
86            clocks = <&mmsys CLK_MM_DISP_CCORR0>;
87            mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
88        };
89    };
90