1*24c81b9eSAnitha Chrisanthus# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*24c81b9eSAnitha Chrisanthus%YAML 1.2 3*24c81b9eSAnitha Chrisanthus--- 4*24c81b9eSAnitha Chrisanthus$id: http://devicetree.org/schemas/display/intel,keembay-msscam.yaml# 5*24c81b9eSAnitha Chrisanthus$schema: http://devicetree.org/meta-schemas/core.yaml# 6*24c81b9eSAnitha Chrisanthus 7*24c81b9eSAnitha Chrisanthustitle: Devicetree bindings for Intel Keem Bay MSSCAM 8*24c81b9eSAnitha Chrisanthus 9*24c81b9eSAnitha Chrisanthusmaintainers: 10*24c81b9eSAnitha Chrisanthus - Anitha Chrisanthus <anitha.chrisanthus@intel.com> 11*24c81b9eSAnitha Chrisanthus - Edmond J Dea <edmund.j.dea@intel.com> 12*24c81b9eSAnitha Chrisanthus 13*24c81b9eSAnitha Chrisanthusdescription: | 14*24c81b9eSAnitha Chrisanthus MSSCAM controls local clocks in the display subsystem namely LCD clocks and 15*24c81b9eSAnitha Chrisanthus MIPI DSI clocks. It also configures the interconnect between LCD and 16*24c81b9eSAnitha Chrisanthus MIPI DSI. 17*24c81b9eSAnitha Chrisanthus 18*24c81b9eSAnitha Chrisanthusproperties: 19*24c81b9eSAnitha Chrisanthus compatible: 20*24c81b9eSAnitha Chrisanthus items: 21*24c81b9eSAnitha Chrisanthus - const: intel,keembay-msscam 22*24c81b9eSAnitha Chrisanthus - const: syscon 23*24c81b9eSAnitha Chrisanthus 24*24c81b9eSAnitha Chrisanthus reg: 25*24c81b9eSAnitha Chrisanthus maxItems: 1 26*24c81b9eSAnitha Chrisanthus 27*24c81b9eSAnitha Chrisanthus reg-io-width: 28*24c81b9eSAnitha Chrisanthus const: 4 29*24c81b9eSAnitha Chrisanthus 30*24c81b9eSAnitha Chrisanthusrequired: 31*24c81b9eSAnitha Chrisanthus - compatible 32*24c81b9eSAnitha Chrisanthus - reg 33*24c81b9eSAnitha Chrisanthus - reg-io-width 34*24c81b9eSAnitha Chrisanthus 35*24c81b9eSAnitha ChrisanthusadditionalProperties: false 36*24c81b9eSAnitha Chrisanthus 37*24c81b9eSAnitha Chrisanthusexamples: 38*24c81b9eSAnitha Chrisanthus - | 39*24c81b9eSAnitha Chrisanthus msscam:msscam@20910000 { 40*24c81b9eSAnitha Chrisanthus compatible = "intel,keembay-msscam", "syscon"; 41*24c81b9eSAnitha Chrisanthus reg = <0x20910000 0x30>; 42*24c81b9eSAnitha Chrisanthus reg-io-width = <4>; 43*24c81b9eSAnitha Chrisanthus }; 44